SAF-XC164LM-8F40F AA Infineon Technologies, SAF-XC164LM-8F40F AA Datasheet - Page 38
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SAF-XC164LM-8F40F AA
Manufacturer Part Number
SAF-XC164LM-8F40F AA
Description
IC MCU 16BIT 64KB FLASH TQFP64-8
Manufacturer
Infineon Technologies
Series
XC16xr
Datasheet
1.SAF-XC164LM-16F40F_BA.pdf
(61 pages)
Specifications of SAF-XC164LM-8F40F AA
Core Processor
C166SV2
Core Size
16-Bit
Speed
40MHz
Connectivity
SPI, UART/USART
Peripherals
PWM, WDT
Number Of I /o
47
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.7 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LFQFP
For Use With
MCBX167-NET - BOARD EVAL INFINEON CAN/ETHRNTMCBXC167-BASIC - BOARD EVAL BASIC INFINEON XC16X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Other names
SAF-XC164LM-8F40FAACT
SAF-XC164LM-8F40FAACT
SAF-XC164LM-8F40FAAINCT
SAF-XC164LM-8F40FAACT
SAF-XC164LM-8F40FAAINCT
XC164LM
Derivatives
Functional Description
3.11
Clock Generation
The Clock Generation Unit uses a programmable on-chip PLL with multiple prescalers
f
to generate the clock signals for the XC164LM with high flexibility. The master clock
MC
f
is the reference clock signal and is output to the external system. The CPU clock
CPU
f
and the system clock
are derived from the master clock either directly (1:1) or via a
SYS
f
f
f
2:1 prescaler (
=
=
/ 2). See also
Section
4.3.1.
SYS
CPU
MC
The on-chip oscillator can drive an external crystal or accepts an external clock signal.
The oscillator clock frequency can be multiplied by the on-chip PLL (by a programmable
factor) or can be divided by a programmable prescaler factor.
If the bypass mode is used (direct drive or prescaler) the PLL can deliver an independent
clock to monitor the clock signal generated by the on-chip oscillator. This PLL clock is
independent from the XTAL1 clock. When the expected oscillator clock transitions are
missing the Oscillator Watchdog (OWD) activates the PLL Unlock/OWD interrupt node
and supplies the CPU with an emergency clock, the PLL clock signal. Under these
circumstances the PLL will oscillate with its basic frequency.
The oscillator watchdog can be disabled by switching the PLL off. This reduces power
consumption, but also no interrupt request will be generated in case of a missing
oscillator clock.
Data Sheet
36
V1.2, 2007-03