DS89C420-QCS Maxim Integrated Products, DS89C420-QCS Datasheet - Page 24
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DS89C420-QCS
Manufacturer Part Number
DS89C420-QCS
Description
IC MCU 50MHZ ULTRA HS 44-PLCC
Manufacturer
Maxim Integrated Products
Series
89Cr
Datasheet
1.DS89C420-QCS.pdf
(47 pages)
Specifications of DS89C420-QCS
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
EBI/EMI, SIO, UART/USART
Peripherals
Power-Fail Reset, WDT
Number Of I /o
32
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
44-LCC, 44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Read Address 30,
Write Encryption
Table 4. Parallel Programming Instruction Set
Control Register
Control Register
1)
2)
3)
4)
Note 1: P3.2 is pulled low during programming to indicate Busy. P3.2 is pulled high again when programming is completed to indicate Ready.
Note 2: P3.0 is pulled high during programming to indicate an error.
DATA POINTER INCREMENT/DECREMENT AND OPTIONS
The DS89C420 incorporates
increment/decrement. Data pointer increment/decrement bits ID0 and ID1 (DPS.6 and DPS.7) define how the INC
DPTR instruction functions in relation to the active DPTR (selected by the SEL bit). Setting ID0 = 1 and SEL = 0
enables the decrement operation for DPTR, and execution of the INC DPTR instruction decrements the DPTR
contents by 1. Similarly, setting ID1 = 1 and SEL = 1 enables the decrement operation for DPTR1, and execution of
the INC DPTR instruction decrements the DPTR1 contents by 1. With this feature, the user can configure the data
pointers to operate in four ways for the INC DPTR instruction:
INSTRUCTION
Read Lock Bits
Read Program
Write Program
Erase Option
Mass erase requires an active-low PROG pulse width of 828ms.
Erase option control register requires an active-low PROG pulse width of 828ms.
Byte program requires an active-low PROG pulse width of 100ms max.
PROG is weakly pulled to a high internally.
Write Option
Mass Erase
31, 60, FC
Write LB1
Write LB2
Write LB3
Memory
Memory
Array
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
P2.5:0,
P1.7:0
ADDR
ADDR
ADDR
ADDR
ID1
0
0
1
1
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
P0.7:0
DOUT
DOUT
DOUT
ID0
a hardware feature to
DIN
DIN
DIN
0
1
0
1
Decrement DPTR
Decrement DPTR
PROG
Increment DPTR
Increment DPTR
PL
PL
PL
PL
PL
PL
PL
PL
H
H
H
(4)
(4)
(4)
(1)
(3)
(3)
(3)
(3)
(3)
(3)
(2)
SEL = 0
P2.6
24 of 47
H
H
H
H
H
L
L
L
L
L
L
P2.7
H
H
H
H
H
L
L
L
L
L
L
assist applications
P3.6
Decrement DPTR1
Decrement DPTR1
Increment DPTR1
Increment DPTR1
H
H
H
H
L
L
L
L
L
L
L
DS89C420 Ultra-High-Speed Microcontroller
SEL = 1
P3.7
H
H
H
H
H
H
L
L
L
L
L
Mass erase the 16k x 8 program
memory, the security block and the bank
select. The contents of every memory
location is returned to FFh.
Program the 16k program memory.
Verify the 16k program memory.
Program the 64 byte encryption array.
Program LB1 to logic 0.
Program LB2 and LB1 to 00b.
Program LB3, LB2, and LB1 to 000b.
Verify the lock bits. The lock bits are at
address 40h and the three LSBs of the
DOUT are the logic value of the lock bits
LB3, LB2, and LB1, respectively.
Program the option control register. Bit 3
of the DIN represents the watchdog
POR default setting.
Erase the option control register. This
operation disables the watch-dog reset
function on power-up.
30h = Manufacturer ID
31h = Device ID
60h = Device extension
FCh = Verify the option control register.
Bit 3 of the DOUT is the logic value of
the watchdog POR.
that
OPERATION
require
data
pointer