MC9S08DV60MLF Freescale Semiconductor, MC9S08DV60MLF Datasheet - Page 54
![IC MCU 60K FLASH 3K RAM 48-LQFP](/photos/12/46/124636/mc9s08dv60amlf_sml.jpg)
MC9S08DV60MLF
Manufacturer Part Number
MC9S08DV60MLF
Description
IC MCU 60K FLASH 3K RAM 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DV60MLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DV60MLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 4 Memory
54
3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its
4. Wait until the FCCF bit in FSTAT is set. As soon as FCCF= 1, the operation has completed
address and data information).
A partial command sequence can be aborted manually by writing a 0 to FCBEF any time after the
write to the memory array and before writing the 1 that clears FCBEF and launches the complete
command. Aborting a command in this way sets the FACCERR access error flag which must be
cleared before starting a new command.
A strictly monitored procedure must be obeyed or the command will not be accepted. This
minimizes the possibility of any unintended changes to the memory contents. The command
complete flag (FCCF) indicates when a command is complete. The command sequence must be
completed by clearing FCBEF to launch the command.
of the commands except for burst programming and sector erase abort.
successfully.
PROGRAM AND
ERASE FLOW
Figure 4-2. Program and Erase Flowchart
MC9S08DV60 Series Data Sheet, Rev 3
0
WRITE COMMAND TO FCMD
WRITE TO FLASH TO BUFFER
TO LAUNCH COMMAND
AND CLEAR FCBEF
WRITE TO FCDIV
ADDRESS AND DATA
WRITE 1 TO FCBEF
CLEAR ERROR
FACCERR?
FPVIOL OR
FACCERR?
START
FCCF?
DONE
1
NO
(1)
(2)
0
Figure 4-2
YES
(2)
before checking FCBEF or FCCF.
(1)
Wait at least four bus cycles
after reset.
Required only once
ERROR EXIT
is a flowchart for executing all
Freescale Semiconductor
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