MC9S08DV60MLF Freescale Semiconductor, MC9S08DV60MLF Datasheet - Page 339
![IC MCU 60K FLASH 3K RAM 48-LQFP](/photos/12/46/124636/mc9s08dv60amlf_sml.jpg)
MC9S08DV60MLF
Manufacturer Part Number
MC9S08DV60MLF
Description
IC MCU 60K FLASH 3K RAM 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DV60MLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
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16.6.2.1.2
When CPWMS=1, TOF gets set when the timer counter changes direction from up-counting to
down-counting at the end of the terminal count (the value in the modulo register). In this case the TOF
corresponds to the end of a PWM period.
16.6.2.2
The meaning of channel interrupts depends on the channel’s current mode (input-capture, output-compare,
edge-aligned PWM, or center-aligned PWM).
16.6.2.2.1
When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select no edge
(off), rising edges, falling edges or any edge as the edge which triggers an input capture event. When the
selected edge is detected, the interrupt flag is set. The flag is cleared by the two-step sequence described
in
16.6.2.2.2
When a channel is configured as an output compare channel, the interrupt flag is set each time the main
timer counter matches the 16-bit value in the channel value register. The flag is cleared by the two-step
sequence described
16.6.2.2.3
For channels configured for PWM operation there are two possibilities. When the channel is configured
for edge-aligned PWM, the channel flag gets set when the timer counter matches the channel value register
which marks the end of the active duty cycle period. When the channel is configured for center-aligned
PWM, the timer count matches the channel value register twice during each PWM cycle. In this CPWM
case, the channel flag is set at the start and at the end of the active duty cycle period which are the times
when the timer counter matches the channel value register. The flag is cleared by the two-step sequence
described
16.7
Freescale Semiconductor
Section 16.6.2, “Description of Interrupt Operation.”
1. Write to TPMxCNTH:L registers
2. Read of TPMxCNTH:L registers
(TPMxCNTH:TPMxCNTL)) [SE110-TPM case 7]
Any write to TPMxCNTH or TPMxCNTL registers in TPM v3 clears the TPM counter
(TPMxCNTH:L) and the prescaler counter. Instead, in the TPM v2 only the TPM counter is cleared
in this case.
(TPMxCNTH:TPMxCNTL))
— In TPM v3, any read of TPMxCNTH:L registers during BDM mode returns the value of the
The Differences from TPM v2 to TPM v3
Section 16.6.2, “Description of Interrupt Operation.”
TPM counter that is frozen. In TPM v2, if only one byte of the TPMxCNTH:L registers was
read before the BDM mode became active, then any read of TPMxCNTH:L registers during
Channel Event Interrupt Description
Center-Aligned PWM Case
Input Capture Events
Output Compare Events
PWM End-of-Duty-Cycle Events
Section 16.6.2, “Description of Interrupt Operation.”
MC9S08DV60 Series Data Sheet, Rev 3
(Section 16.3.2, “TPM-Counter Registers
(Section 16.3.2, “TPM-Counter Registers
Chapter 16 Timer/PWM Module (S08TPMV3)
339
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