C8051F537-IT Silicon Laboratories Inc, C8051F537-IT Datasheet - Page 150

• Manufacturer Part Number: C8051F537-IT
• Description: IC 8051 MCU 2K FLASH 20TSSOP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F53xr

Specifications of C8051F537-IT

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.25 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 336-1401

C8051F52x/F52xA/F53x/F53xA
16. Enhanced Serial Peripheral Interface (SPI0)
The Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus.
SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple mas-
ters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select
SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding conten-
tion on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be
configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional general pur-
pose port I/O pins can be used to select multiple slave devices in master mode.
150
SYSCLK
Clock Divide
SPI0CKR
SFR Bus
SPI0DAT
Logic
Write
Transmit Data Buffer
Receive Data Buffer
7
Figure 16.1. SPI Block Diagram
6
Shift Register
5
SPI CONTROL LOGIC
4
3
Data Path
2
SFR Bus
SPI0CFG
Control
SPI0DAT
1
SPI0DAT
Read
0
Rev. 1.3
Tx Data
Rx Data
Pin Interface
Control
Control
Logic
Pin
SPI0CN
MOSI
MISO
SCK
NSS
O
C
R
S
S
B
A
R
SPI IRQ
Port I/O