MC9S08RD32CPE Freescale Semiconductor, MC9S08RD32CPE Datasheet - Page 153

• Manufacturer Part Number: MC9S08RD32CPE
• Description: IC MCU 32K FLASH 2K RAM 28-DIP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08RD32CPE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

12.2.4
This register has eight read-only status flags. Writes have no effect. Special software sequences (which do
not involve writing to this register) are used to clear these status flags.
Freescale Semiconductor
Reset
TDRE
Field
RWU
Field
SBK
TC
1
0
7
6
W
R
TDRE
SCI Status Register 1 (SCI1S1)
Receiver Wakeup Control — This bit can be written to 1 to place the SCI receiver in a standby state where it
waits for automatic hardware detection of a selected wakeup condition. The wakeup condition is either an idle
line between messages (WAKE = 0, idle-line wakeup), or a logic 1 in the most significant data bit in a character
(WAKE = 1, address-mark wakeup). Application software sets RWU and (normally) a selected hardware
condition automatically clears RWU. Refer to
0 Normal SCI receiver operation.
1 SCI receiver in standby waiting for wakeup condition.
Send Break — Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional
break characters of 10 or 11 bit times of logic 0 are queued as long as SBK = 1. Depending on the timing of the
set and clear of SBK relative to the information currently being transmitted, a second break character may be
queued before software clears SBK. Refer to
0 Normal transmitter operation.
1 Queue break character(s) to be sent.
Transmit Data Register Empty Flag — TDRE is set immediately after reset and when a transmit data value
transfers from the transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. To
clear TDRE, read SCI1S1 with TDRE = 1 and then write to the SCI data register (SCI1D).
0 Transmit data register (buffer) full.
1 Transmit data register (buffer) empty.
Transmission Complete Flag — TC is set immediately after reset and when TDRE = 1 and no data, preamble,
or break character is being transmitted.
0 Transmitter active (sending data, a preamble, or a break).
1 Transmitter idle (transmission activity complete).
TC is cleared automatically by reading SCI1S1 with TC = 1 and then doing one of the following three things:
1
7
• Write to the SCI data register (SCI1D) to transmit new data
• Queue a preamble by changing TE from 0 to 1
• Queue a break character by writing 1 to SBK in SCI1C2
= Unimplemented or Reserved
Table 12-4. SCI1C2 Register Field Descriptions (continued)
TC
1
6
Table 12-5. SCI1S1 Register Field Descriptions
Figure 12-7. SCI Status Register 1 (SCI1S1)
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
RDRF
0
5
IDLE
Section 12.3.3.2, “Receiver Wakeup
Section 12.3.2.1, “Send Break and Queued
0
4
Description
Description
OR
3
0
Serial Communications Interface (S08SCIV1)
NF
0
2
Operation,” for more details.
FE
Idle,” for more details.
0
1
PF
0
0
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