MC908GR16ACFAER Freescale Semiconductor, MC908GR16ACFAER Datasheet - Page 165

• Manufacturer Part Number: MC908GR16ACFAER
• Description: IC MCU 16K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR16ACFAER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.8.7 ESCI Baud Rate Register
The ESCI baud rate register (SCBR) together with the ESCI prescaler register selects the baud rate for
both the receiver and the transmitter.
LINT — LIN Break Symbol Transmit Enable
LINR — LIN Break Symbol Receiver Bits
Freescale Semiconductor
This read/write bit selects the enhanced ESCI features for master nodes in the local interconnect
network (LIN) protocol (version 1.2) as shown in
This read/write bit selects the enhanced ESCI features for slave nodes in the local interconnect
network (LIN) protocol as shown in
In LIN (version 1.2) systems, the master node transmits a break character which will appear as
11.05–14.95 dominant bits to the slave node. A data character of 0x00 sent from the master might
appear as 7.65–10.35 dominant bit times. This is due to the oscillator tolerance requirement that the
slave node must be within ±15% of the master node's oscillator. Since a slave node cannot know if it
is running faster or slower than the master node (prior to synchronization), the LINR bit allows the slave
Address:
There are two prescalers available to adjust the baud rate. One in the ESCI
baud rate register and one in the ESCI prescaler register.
LIN master nodes require significantly tighter timing tolerances than slave
nodes. Be sure to consult the current LIN specification to ensure that timing
requirements are met properly. Generally, these timing tolerances require
crystals or oscillators to be used, rather than internal clocking circuits.
Reset:
Read:
Write:
$0019
LINT
Bit 7
LINT
LINR
R
0
0
1
1
0
1
1
Figure 14-17. ESCI Baud Rate Register (SCBR)
Table 14-6. ESCI LIN Master Node Control Bits
Table 14-7. ESCI LIN Slave Node Control Bits
= Reserved
M
X
0
1
M
X
0
1
LINR
6
0
MC68HC908GR16A Data Sheet, Rev. 1.0
Normal ESCI functionality
13-bit break generation enabled for LIN transmitter
14-bit break generation enabled for LIN transmitter
Normal ESCI functionality
11-bit break detect enabled for LIN receiver
12-bit break detect enabled for LIN receiver
Table
SCP1
5
0
14-7. Reset clears LINR.
NOTE
NOTE
SCP0
4
0
Table
Functionality
Functionality
14-6. Reset clears LINT.
R
3
0
SCR2
2
0
SCR1
1
0
SCR0
Bit 0
0
I/O Registers
165