M30855FJGP#D3 Renesas Electronics America, M30855FJGP#D3 Datasheet - Page 322

MCU 3/5V 512K I-TEMP 144-LQFP

M30855FJGP#D3

Manufacturer Part Number
M30855FJGP#D3
Description
MCU 3/5V 512K I-TEMP 144-LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet

Specifications of M30855FJGP#D3

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Part Number
Manufacturer
Quantity
Price
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Part Number:
M30855FJGP#D3M30855FJGP
Manufacturer:
RENESAS/瑞萨
Quantity:
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Part Number:
M30855FJGP#D3M30855FJGP#U3
Manufacturer:
Renesas Electronics America
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Part Number:
M30855FJGP#D3M30855FJGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
M
R
R
e
E
3
. v
J
2
Figure 22.18 SR Waveform Output Mode
0
C
1
9
0 .
8 /
B
0
3
5
0
3
G
J
7
u
o r
0 -
. l
u
0
1
(1) Free-Running Operation
(2) The Base Timer is Reset when the Base Timer Matches the G1PO0 Register
p
, 1
0
3
(
(The RST2 to RST0 bits in the G1BCR1 register are set to "00
2
(The RST1 bit is set to "1" and the RST2 bit is set to "0")
M
Base Timer
OUTC1j pin
OUTC1j pin
PO1jR bit in the
IIOiIR register
PO1kR bit in the
IIOiIR register
Base timer
OUTC1j pin
PO1jR bit in the
IIOiIR register
PO1kR bit in the
IIOiIR register
0
3
0
NOTES:
The diagram above applies under the following condition:
The diagram above applies to the following conditions:
2
5
• The IVL bit in the G1POCRj register is set to "0" ("L" output as default value).
• The UD1 and UD0 bits in the G1BCR1 register are set to "00
• m<n<p+2
C
The INV bit is set to "0" (not inversed).
• The RST2 and RST1 bits in the G1BCR1 register are set to "00
• m<n
8 /
2. Waveform output when the INV bit is set to "0" (not inversed) and the IVL bit is set to "1"
1. Waveform output when the INV bit in the G1POCRj register is set to "0" (not inversed)
Page 297
and the UD1 and UD0 bits to "00
, 5
("H" output as default value).
and the IVL bit is set to "0" (output "L" as default value).
(1)
(2)
M
0000
FFFF
0000
3
p+2
"H"
"L"
"1"
"0"
"1"
"0"
2
16
m
n
C
16
"H"
"L"
"H"
"L"
"1"
"0"
"1"
"0"
16
i=0 to 4, 8 to 10; j=2, 4, 6;
m : Setting value of the G1POj register, 0000
n: Setting value of the G1POk register, 0000
p: Setting value of the G1PO0 register, 0001
i=0 to 4, 8 to 10; j=0, 2, 4, 6; k=j+1
m : Setting value of the G1POj register, 0000
n: Setting value of the G1POk register, 0000
m
n
f o
8 /
4
5
9
) T
4
n-m
f
BT1
n-m
f
BT1
Write "0" by program
if setting to "0"
2
Write "0" by program
if setting to "0"
" (counter increment mode).
p+2-n+m
k=j+1
f
65536
BT1
Write "0" by program
if setting to "0"
f
BT1
65536-n+m
f
Write "0" by program
if setting to "0"
BT1
22. Intelligent I/O (Waveform Generating Function)
16
16
16
16
16
to FFFF
to FFFF
to FFFD
to FFFF
to FFFF
2
" (counter increment mode).
2
" (no base timer reset)
16
16
16
16
16
2
")

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