MC908GR48AVFAE Freescale Semiconductor, MC908GR48AVFAE Datasheet - Page 237
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MC908GR48AVFAE
Manufacturer Part Number
MC908GR48AVFAE
Description
IC MCU 8BIT 48K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GR32ACFJE.pdf
(314 pages)
Specifications of MC908GR48AVFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GR48AVFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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CHxF — Channel x Flag Bit
CHxIE — Channel x Interrupt Enable Bit
MSxB — Mode Select Bit B
MSxA — Mode Select Bit A
Freescale Semiconductor
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIM1 counter registers matches the value in the TIM1 channel x registers.
Clear CHxF by reading the TIM1 channel x status and control register with CHxF set and then writing
a 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing
0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of
CHxF.
Reset clears the CHxF bit. Writing a 1 to CHxF has no effect.
This read/write bit enables TIM1 CPU interrupt service requests on channel x. Reset clears the CHxIE
bit.
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM1
channel 0 status and control register.
Setting MS0B disables the channel 1 status and control register and reverts T1CH1 to general-purpose
I/O.
Reset clears the MSxB bit.
When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output
compare/PWM operation. See
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
Figure 17-8. TIM1 Channel Status and Control Registers (T1SC0:T1SC1)
Address: $0025
Address: $0028
Reset:
Reset:
Read:
Read:
Write:
Write:
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
CH0F
CH1F
Bit 7
Bit 7
0
0
0
0
T1SC0
T1SC1
= Unimplemented
CH0IE
CH1IE
6
0
6
0
Table
17-2.
MS0B
5
0
5
0
0
MS0A
MS1A
4
0
4
0
ELS0B
ELS1B
3
0
3
0
ELS0A
ELS1A
2
0
2
0
TOV0
TOV1
1
0
1
0
Input/Output Registers
CH0MAX
CH1MAX
Bit 0
Bit 0
0
0
237
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