MC908GR48AVFAE Freescale Semiconductor, MC908GR48AVFAE Datasheet - Page 197

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MC908GR48AVFAE

Manufacturer Part Number
MC908GR48AVFAE
Description
IC MCU 8BIT 48K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908GR48AVFAE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MC908GR48AVFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
14.6.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run.
the timing for wait mode entry.
A module that is active during wait mode can wakeup the CPU with an interrupt if the interrupt is enabled.
Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.
In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the
module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
Wait mode also can be exited by a reset or break. A break interrupt during wait mode sets the SIM break
stop/wait bit, SBSW, in the SIM break status register (BSR). If the COP disable bit, COPD, in the
CONFIG1 register is 0, then the computer operating properly module (COP) is enabled and remains
active in wait mode.
Figure 14-17
Freescale Semiconductor
and
EXITSTOPWAIT
Note: EXITSTOPWAIT = RST pin, CPU interrupt, or break interrupt
CGMXCLK
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
R/W
Figure 14-18
IAB
IDB
Note:
RST
IDB
IAB
IDB
IAB
Figure 14-17. Wait Recovery from Interrupt or Break
$A6
Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
WAIT ADDR
Figure 14-18. Wait Recovery from Internal Reset
$A6
$6E0B
$A6
show the timing for WAIT recovery.
PREVIOUS DATA
Figure 14-16. Wait Mode Entry Timing
$6E0B
$A6
$A6
WAIT ADDR + 1
$A6
CYCLES
$6E0C
32
NEXT OPCODE
$01
$00FF
CYCLES
32
$0B
SAME
$00FE
$6E
SAME
RST VCT H
$00FD
SAME
RST VCT L
$00FC
SAME
Figure 14-16
Low-Power Modes
shows
197

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