EG80C196EA Intel, EG80C196EA Datasheet - Page 17

• Manufacturer Part Number: EG80C196EA
• Description: IC MPU 16-BIT 5V 40MHZ 160-QFP
• Manufacturer: Intel
• Series: 80Cr

Specifications of EG80C196EA

• Core Processor: MCS 96
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: SIO
• Peripherals: PWM, WDT
• Number Of I /o: 83
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 864391

6.2
Preliminary Datasheet
Table 7. AC Characteristics, Multiplexed Bus Mode (Sheet 1 of 2)
AC Characteristics — Multiplexed Bus Mode
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.
F
f
t
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
NOTES:
1. 20 MHz is the maximum input frequency when using an external crystal oscillator; however, 40 MHz can be
2. If wait states are used, add 2t
3. Assuming back-to-back bus cycles.
4. When forcing wait states using the BUSCON register, add 2t
5. Exceeding the maximum specification causes additional wait states.
6. 8-bit bus only.
7. The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed wait
8. Device is static by design but has been tested only down to 20 MHz.
9. Assumes CLKOUT is operating in divide-by-two mode (f/2).
Symbol
XTAL1
AVDV
RLDV
CHDV
RHDZ
RXDX
XHCH
CLCL
CHCL
CLLH
LLCH
LHLH
LHLL
AVLL
LLAX
LLRL
RLCL
RLRH
RHLH
RLAZ
LLWL
QVWH
CHWH
WLWH
applied with an external clock source.
state is required.
Frequency on XTAL1, PLL in 1x mode
Frequency on XTAL1, PLL in 2x mode
Operating frequency, f = F
Operating frequency, f = 2F
Period, t = 1/f
Address Valid to Input Data Valid
RD# Low to Input Data Valid
CLKOUT High to Input Data valid
RD# High to Input Data Float
Data Hold after RD# Inactive
XTAL1 Rising Edge to CLKOUT High or Low
CLKOUT Cycle Time
CLKOUT High Period
CLKOUT Falling to ALE Rising
ALE Falling to CLKOUT Rising
ALE Cycle Time
ALE High Period
Address Setup to ALE Low
Address Hold after ALE Low
ALE Low to RD# Low
RD# Low to CLKOUT Low
RD# Low to RD# High
RD# High to ALE Rising
RD# Low to Address Float
ALE Low to WR# Low
Data Stable to WR# Rising Edge
CLKOUT High to WR# Rising Edge
WR# Low to WR# High
n , where n = number of wait states.
Parameter
XTAL1
XTAL1
; PLL in 1x mode
; PLL in 2x mode
n.
t – 10
t – 10
t – 15
t – 15
t – 15
t – 12
t – 12
t – 14
t – 10
– 10
– 10
– 10
t – 5
– 10
Min
20
20
10
25
0
3
80C196EA - Commercial
2t
4t
3t – 40
2t – 35
t – 18
t + 10
t + 10
t + 15
Max
t + 5
40
20
40
50
50
10
10
10
10
5
MHz (1, 8)
MHz (8)
MHz (8)
ns (2)
ns (2)
ns (9)
ns (9)
ns (9)
ns (9)
ns (9)
ns (9)
ns (2)
ns (9)
ns (2)
ns (3)
ns (
ns (9)
ns (2)
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
)
13