EE80C196MC Intel, EE80C196MC Datasheet - Page 7

• Manufacturer Part Number: EE80C196MC
• Description: IC MPU 16-BIT 5V 16MHZ 84-PLCC
• Manufacturer: Intel
• Series: 80Cr

Specifications of EE80C196MC

• Core Processor: MCS 96
• Core Size: 16-Bit
• Speed: 16MHz
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Type: ROMless
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Connectivity: -
• Other names: 863951

PIN DESCRIPTIONS
ACH0–ACH12
(P0 0–P0 7 P1 0– P1 4)
ANGND
ALE ADV(P5 0)
BHE WRH (P5 5)
BUSWIDTH (P5 7)
CAPCOMP0 – CAPCOMP3
(P2 0–P2 3)
CLKOUT
COMPARE0 – COMPARE3
(P2 4–P2 7)
EA
EXTINT
INST (P5 1)
NMI
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
Symbol
(Alphabetically Ordered)
Analog inputs to the on-chip A D converter ACH0 – 7 share the input pins
with P0 0– 7 and ACH8 – 12 share pins with P1 0 – 4 If the A D is not used
the port pins can be used as standard input ports
Reference ground for the A D converter Must be held at nominally the
same potential as V
Address Latch Enable or Address Valid output as selected by CCR Both
options allow a latch to demultiplex the address data bus on the signal’s
falling edge When the pin is ADV it goes inactive (high) at the end of the
bus cycle ALE ADV is active only during external memory accesses Can be
used as standard I O when not used as ALE ADV
Byte High Enable or Write High output as selected by the CCR BHE will go
low for external writes to the high byte of the data bus WRH will go low for
external writes where an odd byte is being written BHE WRH is activated
only during external memory writes
Input for bus width selection If CCR bits 1 and 2
controls the bus width of the bus cycle in progress If BUSWIDTH is low an
8-bit cycle occurs If it is high a 16-bit cycle occurs This pin can be used as
standard I O when not used as BUSWIDTH
The EPA Capture Compare pins These pins share P2 0 – P2 3 If not used
for the EPA they can be configured as standard I O pins
Output of the internal clock generator The frequency is
frequency It has a 50% duty cycle
The EPA Compare pins These pins share P2 4 – P2 7 If not used for the
EPA they can be configured as standard I O pins
External Access enable pin EA
external to the chip EA
to 5FFFH to be from the on-chip OTPROM QROM EA
execution to begin in the programming mode EA is latched at reset
A programmable input on this pin causes a maskable interrupt vector
through memory location 203CH The input may be selected to be a
positive negative edge or a high low level using WG PROTECT (1FCEH)
INST is high during the instruction fetch from the external memory and
throughout the bus cycle It is low otherwise This pin can be configured as
standard I O if not used as INST
A positive transition on this pin causes a non-maskable interrupt which
vectors to memory location 203EH If not used it should be tied to V
be used by Intel Evaluation boards
8-bit high impedance input-only port Also used as A D converter inputs
Port0 pins should not be left floating These pins also used to select
programming modes in the OTPROM devices
5-bit high impedance input-only port P1 0 – P1 4 are also used as A D
converter inputs In addition P1 2 and P1 3 can be used as Timer 1 clock
input and direction select respectively
8-bit bidirectional I O port All of the Port2 pins are shared with the EPA I O
pins (CAPCOMP0 – 3 and COMPARE0 – 3)
8-bit bidirectional I O ports with open drain outputs These pins are shared
with the multiplexed address data bus which uses strong internal pullups
8-bit bidirectional I O port 7 of the pins are shared with bus control signals
(ALE INST WR RD BHE READY BUSWIDTH) Can be used as standard
I O
SS
e
1 causes memory accesses from location 2000H
e
Function
0 causes all memory accesses to be
e
1 this pin dynamically
e
12 5V causes
of the oscillator
8XC196MC
SS
May
7