MPC564CVR40 Freescale Semiconductor, MPC564CVR40 Datasheet - Page 223

• Manufacturer Part Number: MPC564CVR40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CVR40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Section 4.6.2.3, “Region Attribute Registers
Attribute Register
4.6
4.6.1
The BBC consists of three separately addressable sections within the internal chip address space:
4.6.1.1
Freescale Semiconductor
1. BBC and IMPU control registers. These are mapped in the SPR registers area and may be
2. Decompressor vocabulary RAM (DECRAM). The DECRAM array occupies the 2-Kbyte physical
3. Decompressor class configuration registers (DCCR) block. It consists of 15 decompression class
SPR Number
(Decimal)
programmed by using the RCPU mtspr/mfspr instructions.
memory (8 Kbytes of the MPC561/MPC563 address space is allocated for DECRAM).
configuration registers. These registers are available for word wide read/write accesses through
U-bus. The registers occupy a 64-byte physical block (8-Kbyte chip address space is allocated for
the register block).
528
529
560
BBC Programming Model
Address Map
BBC Special Purpose Registers (SPRs)
(MI_GRA)” for details.
Access (Hex)
Address for
External
0x2100
0x2300
0x2110
Master
0x2F 8000
0x2F 87FF
0x2F 8800
0x2F 9FFF
0x2F A000
0x2F A03F
Figure 4-6. MPC561/MPC563 Memory Map
IMPU Global Region Attribute Register (MI_GRA). See
descriptions.
External Interrupt Relocation Table Base Address Register (EIBADR). See
Table 4-9
BBC Module Configuration Register (BBCMCR). See
MPC561/MPC563 Reference Manual, Rev. 1.2
for bits descriptions.
Table 4-3. BBC SPRs
(MI_RA[0:3]),” and
Reserved
DCCR0 – DCCR15
DECRAM
2 Kbytes
Register Name
Section 4.6.2.4, “Global Region
Table 4-4
Table 4-8
Burst Buffer Controller 2 Module
for bits descriptions
for bits
4-17