MC9S08GT16CFDE Freescale Semiconductor, MC9S08GT16CFDE Datasheet - Page 211
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MC9S08GT16CFDE
Manufacturer Part Number
MC9S08GT16CFDE
Description
IC MCU 16K FLASH 20MHZ 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.M68EVB908GB60E.pdf
(290 pages)
Specifications of MC9S08GT16CFDE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
For Use With
M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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13.4
The IIC generates a single interrupt.
An interrupt from the IIC is generated when any of the events in
is set. The interrupt is driven by bit IICIF (of the IIC status register) and masked with bit IICIE (of the IIC
control register). The IICIF bit must be cleared by software by writing a one to it in the interrupt routine.
The user can determine the interrupt type by reading the status register.
13.4.1
The TCF (transfer complete flag) bit is set at the falling edge of the 9th clock to indicate the completion of
byte transfer.
13.4.2
When its own specific address (IIC address register) is matched with the calling address, the IAAS bit in
status register is set. The CPU is interrupted provided the IICIE is set. The CPU must check the SRW bit
and set its Tx mode accordingly.
13.4.3
The IIC is a true multi-master bus that allows more than one master to be connected on it. If two or more
masters try to control the bus at the same time, the relative priority of the contending masters is determined
by a data arbitration procedure. The IIC module asserts this interrupt when it loses the data arbitration
process and the ARBL bit in the status register is set.
Arbitration is lost in the following circumstances:
This bit must be cleared by software by writing a one to it.
Freescale Semiconductor
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•
•
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SDA sampled as a low when the master drives a high during an address or data transmit cycle.
SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive
cycle.
A START cycle is attempted when the bus is busy.
A repeated START cycle is requested in slave mode.
A STOP condition is detected when the master did not request it.
Interrupts
Byte Transfer Interrupt
Address Detect Interrupt
Arbitration Lost Interrupt
Complete 1-byte transfer
Match of received calling
Interrupt Source
Arbitration Lost
address
MC9S08GB/GT Data Sheet, Rev. 2.3
Table 13-1. Interrupt Summary
Status
ARBL
IAAS
TCF
Flag
IICIF
IICIF
IICIF
Table 13-1
Local Enable
IICIE
IICIE
IICIE
occur provided the IICIE bit
Inter-Integrated Circuit (IIC) Module
211
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