MC68HC908AP8CB Freescale Semiconductor, MC68HC908AP8CB Datasheet - Page 287
MC68HC908AP8CB
Manufacturer Part Number
MC68HC908AP8CB
Description
IC MCU 8K FLASH 8MHZ 42SDIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AP8CFBE.pdf
(324 pages)
Specifications of MC68HC908AP8CB
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SCI, SPI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
32
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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19.3.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the CONFIG1 register.
COPRS — COP Rate Select Bit
COPD — COP Disable Bit
19.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
19.5 Interrupts
The COP does not generate CPU interrupt requests.
19.6 Monitor Mode
When monitor mode is entered with V
on the IRQ1 pin or the RST pin. When monitor mode is entered by having blank reset vectors and not
having V
19.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
Freescale Semiconductor
COPRS selects the COP time out period. Reset clears COPRS.
COPD disables the COP module.
1 = COP time out period = 2
0 = COP time out period = 2
1 = COP module disabled
0 = COP module enabled
TST
on the IRQ1 pin, the COP is automatically disabled until a POR occurs.
Address:
Address:
Reset:
Reset:
Read:
Write:
Read:
Write:
COPRS
$001F
$FFFF
Bit 7
Bit 7
0
Figure 19-2. Configuration Register 1 (CONFIG1)
Figure 19-3. COP Control Register (COPCTL)
LVISTOP
6
0
6
MC68HC908AP Family Data Sheet, Rev. 4
13
18
– 2
– 2
TST
LVIRSTD
4
4
on the IRQ1 pin, the COP is disabled as long as V
ICLK cycles
ICLK cycles
5
0
5
LVIPWRD
Low byte of reset vector
Unaffected by reset
Clear COP counter
4
0
4
LVIREGD
3
0
3
SSREC
2
0
2
STOP
1
0
1
COP Control Register
COPD
Bit 0
Bit 0
0
TST
remains
285
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