MC68HC908AP8CB Freescale Semiconductor, MC68HC908AP8CB Datasheet - Page 268
MC68HC908AP8CB
Manufacturer Part Number
MC68HC908AP8CB
Description
IC MCU 8K FLASH 8MHZ 42SDIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AP8CFBE.pdf
(324 pages)
Specifications of MC68HC908AP8CB
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SCI, SPI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
32
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Input/Output (I/O) Ports
PTC[7:0] — Port C Data Bits
IRQ2 — IRQ2 input pin
MISO, MOSI, SS, and SPSCK — SPI Data I/O, Select, and Clock Pins
SCTxD and SCRxD — IrSCI Transmit and Receive Data
16.4.2 Data Direction Register C (DDRC)
Data direction register C determines whether each port C pin is an input or an output. Writing a logic 1 to
a DDRC bit enables the output buffer for the corresponding port C pin; a logic 0 disables the output buffer.
DDRC[7:0] — Data Direction Register C Bits
Figure 16-11
266
These read/write bits are software-programmable. Data direction of each port C pin is under the control
of the corresponding bit in data direction register C. Reset has no effect on port C data.
The PTC0/IRQ2 pin is always available as input pin to the IRQ2 module. Care must be taken to
available unwanted interrupts when this pin is used as general purpose I/O. PTC0/IRQ2 pin has an
internal pullup, and can be disabled by setting the PUC0ENB bit in the IRQ2 status and control register
(INTSCR2).
These pins are the SPI data in/out, select, and clock pins. Setting the SPE bit in the SPI control register
(SPCR) configures PTC2/MISO, PTC3/MOSI, PTC4/SS, and PTC5/SPSCK pins for SPI function and
overrides any control from the port I/O logic.
The SCTxD and SCRxD pins are IRSCI transmit and receive data pins. Setting the ENSCI bit in the
IRSCI control register 1 (IRSCC1) configures the PTC6/SCTxD and PTC7/SCRxD pins for IRSCI
function and overrides any control from the port I/O logic.
These read/write bits control port C data direction. Reset clears DDRC[7:0], configuring all port C pins
as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
shows the port C I/O logic.
Address:
Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
For those devices packaged in a 42-pin shrink dual in-line package, PTC0
and PTC1 are not connected. DDRC0 and DDRC1 should be set to a 1 to
configure PTC0 and PTC1 as outputs.
Reset:
Read:
Write:
DDRC7
$0006
Bit 7
0
Figure 16-10. Data Direction Register C (DDRC)
DDRC6
6
0
MC68HC908AP Family Data Sheet, Rev. 4
DDRC5
5
0
NOTE
NOTE
DDRC4
4
0
DDRC3
3
0
DDRC2
2
0
DDRC1
1
0
Freescale Semiconductor
DDRC0
Bit 0
0
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