MC68HC908AP16CB Freescale Semiconductor, MC68HC908AP16CB Datasheet - Page 188
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MC68HC908AP16CB
Manufacturer Part Number
MC68HC908AP16CB
Description
IC MCU 16K FLASH 8MHZ 42SDIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AP8CFBE.pdf
(324 pages)
Specifications of MC68HC908AP16CB
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SCI, SPI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
32
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Infrared Serial Communications Interface Module (IRSCI)
The SCI transmitter empty bit, SCTE, in IRSCS1 becomes set when the IRSCDR transfers a byte to the
transmit shift register. The SCTE bit indicates that the IRSCDR can accept new data from the internal
data bus. If the SCI transmit interrupt enable bit, SCTIE, in IRSCC2 is also set, the SCTE bit generates
a transmitter interrupt request.
When the transmit shift register is not transmitting a character, the TxD pin goes to the idle condition, logic
1. If at any time software clears the ENSCI bit in IRSCI control register 1 (IRSCC1), the transmitter and
receiver relinquish control of the port pins.
12.5.2.3 Break Characters
Writing a logic 1 to the send break bit, SBK, in IRSCC2 loads the transmit shift register with a break
character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character
length depends on the M bit in IRSCC1. As long as SBK is at logic 1, transmitter logic continuously loads
break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes
transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the
end of a break character guarantees the recognition of the start bit of the next character.
The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a
logic 0 where the stop bit should be.
Receiving a break character has the following effects on SCI registers:
12.5.2.4 Idle Characters
An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends
on the M bit in IRSCC1. The preamble is a synchronizing idle character that begins every transmission.
If the TE bit is cleared during a transmission, the TxD pin becomes idle after completion of the
transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle
character to be sent after the character currently being transmitted.
12.5.2.5 Transmitter Interrupts
The following conditions can generate CPU interrupt requests from the SCI transmitter:
188
•
•
•
•
•
•
Sets the framing error bit (FE) in IRSCS1
Sets the SCI receiver full bit (SCRF) in IRSCS1
Clears the SCI data register (IRSCDR)
Clears the R8 bit in IRSCC3
Sets the break flag bit (BKF) in IRSCS2
May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits
When queueing an idle character, return the TE bit to logic 1 before the stop
bit of the current character shifts out to the TxD pin. Setting TE after the
stop bit appears on TxD causes data previously written to the IRSCDR to
be lost.
Toggle the TE bit for a queued idle character when the SCTE bit becomes
set and just before writing the next byte to the IRSCDR.
MC68HC908AP Family Data Sheet, Rev. 4
NOTE
Freescale Semiconductor
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