MC68HC908AP16CB Freescale Semiconductor, MC68HC908AP16CB Datasheet - Page 104
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MC68HC908AP16CB
Manufacturer Part Number
MC68HC908AP16CB
Description
IC MCU 16K FLASH 8MHZ 42SDIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AP8CFBE.pdf
(324 pages)
Specifications of MC68HC908AP16CB
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SCI, SPI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
32
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC908AP16CB
Manufacturer:
MOTOROLA
Quantity:
100
Part Number:
MC68HC908AP16CB
Manufacturer:
FREESCALE
Quantity:
20 000
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System Integration Module (SIM)
7.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter.
free-running after all reset states.
internal reset recovery sequences.)
7.5 Exception Control
Normal, sequential program execution can be changed in three different ways:
7.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume.
interrupt entry timing, and
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared).
(See
104
INTERRUPT
INTERRUPT
•
•
•
MODULE
MODULE
Figure
I-BIT
I-BIT
Interrupts:
–
–
Reset
Break interrupts
R/W
R/W
IAB
IDB
IAB
IDB
Maskable hardware CPU interrupts
Non-maskable software interrupt instruction (SWI)
7-10.)
DUMMY
DUMMY
Figure 7-9
SP – 4
SP
PC – 1[7:0] PC – 1[15:8]
Figure 7-9. Interrupt Recovery Timing
CCR
(See 7.3.2 Active Resets from Internal Sources
MC68HC908AP Family Data Sheet, Rev. 4
Figure 7-8. Interrupt Entry Timing
SP – 1
SP – 3
shows interrupt recovery timing.
A
SP – 2
SP – 2
(See 7.6.2 Stop Mode
X
X
SP – 3
SP – 1
PC – 1[15:8] PC – 1[7:0]
A
SP – 4
SP
CCR
VECT H
PC
for details.) The SIM counter is
V DATA H
OPCODE
VECT L
PC + 1
OPERAND
V DATA L
for counter control and
Figure 7-8
Freescale Semiconductor
START ADDR
OPCODE
shows
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