HD64F3664H Renesas Electronics America, HD64F3664H Datasheet - Page 53
![IC H8 MCU FLASH 32K 64QFP](/photos/28/61/286103/64-bqfp__prqp0064gb-a_sml.jpg)
HD64F3664H
Manufacturer Part Number
HD64F3664H
Description
IC H8 MCU FLASH 32K 64QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.US3664-BAG1.pdf
(446 pages)
Specifications of HD64F3664H
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3664H H8/3664
Manufacturer:
RENESAS
Quantity:
13
Company:
Part Number:
HD64F3664HJ
Manufacturer:
TI
Quantity:
171
Part Number:
HD64F3664HJ
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Company:
Part Number:
HD64F3664HV
Manufacturer:
ALTERA
Quantity:
101
Company:
Part Number:
HD64F3664HV
Manufacturer:
RENESAS
Quantity:
630
Company:
Part Number:
HD64F3664HV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F3664HV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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2.3.2
Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and
longword data in memory, however word or longword data must begin at an even address. If an
attempt is made to access word or longword data at an odd address, an address error does not
occur, however the least significant bit of the address is regarded as 0, so access begins the
preceding address. This also applies to instruction fetches.
When ER7 (SP) is used as an address register to access the stack, the operand size should be word
or longword.
Memory Data Formats
Data Type
1-bit data
Byte data
Word data
Longword data
Figure 2.6 Memory Data Formats
Address
Address L
Address L
Address 2M
Address 2M+1
Address 2N
Address 2N+1
Address 2N+2
Address 2N+3
MSB
MSB
MSB
7
7
6
Data Format
5
4
Rev. 6.00 Mar. 24, 2006 Page 23 of 412
3
2
1
LSB
LSB
LSB
0
0
REJ09B0142-0600
Section 2 CPU
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