C8051F045 Silicon Laboratories Inc, C8051F045 Datasheet - Page 244
C8051F045
Manufacturer Part Number
C8051F045
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Specifications of C8051F045
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
336-1157
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C8051F040/1/2/3/4/5/6/7
19.3.4. Slave Receiver Mode
Serial data is received on SDA while the serial clock is received on SCL. The SMBus0 interface receives a
START followed by data byte containing the slave address and direction bit. If the received slave address
matches the address held in register SMB0ADR, the interface generates an ACK. SMBus0 will also ACK if
the general call address (0x00) is received and the General Call Address Enable bit (SMB0ADR.0) is set to
logic 1. In this case the data direction bit (R/W) will be logic 0 to indicate a "WRITE" operation. The
SMBus0 interface receives one or more bytes of serial data; after each byte is received, the interface
transmits an ACK or NACK depending on the state of the AA bit in SMB0CN. SMBus0 exits Slave Receiver
Mode after receiving a STOP condition from the master.
244
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
Figure 19.7. Typical Slave Receiver Sequence
SLA
W
Interrupt
A
Data Byte
Rev. 1.5
Interrupt
A
S = START
P = STOP
A = ACK
R = READ
SLA = Slave Address
Data Byte
Interrupt
A
Interrupt
P
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