C8051F045 Silicon Laboratories Inc, C8051F045 Datasheet - Page 240
C8051F045
Manufacturer Part Number
C8051F045
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Specifications of C8051F045
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
336-1157
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C8051F040/1/2/3/4/5/6/7
Figure 19.2 shows a typical SMBus configuration. The SMBus0 interface will work at any voltage between
3.0 V and 5.0 V and different devices on the bus may operate at different voltage levels. The bi-directional
SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage
through a pullup resistor or similar circuit. Every device connected to the bus must have an open-drain or
open-collector output for both the SCL and SDA lines, so that both are pulled high when the bus is free.
The maximum number of devices on the bus is limited only by the requirement that the rise and fall times
on the bus will not exceed 300 ns and 1000 ns, respectively.
19.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
•
•
240
I
System Management Bus Specification -- Version 1.1, SBS Implementers Forum.
2
C Manual (AN10216-01) -- March 24, 2003, Philips Semiconductor.
V
DD
= 5 V
Figure 19.2. Typical SMBus Configuration
V
Master
Device
DD
= 3 V
Rev. 1.5
Device 1
V
Slave
DD
= 5 V
Device 2
V
Slave
DD
= 3 V
SDA
SCL
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