MC912D60ACPV8 Freescale Semiconductor, MC912D60ACPV8 Datasheet - Page 272

• Manufacturer Part Number: MC912D60ACPV8
• Description: IC MCU 6K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912D60ACPV8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Multiple Serial Interface
SC0SR1/SC1SR1 — SCI Status Register 1
Technical Data
272
RESET:
TDRE
Bit 7
1
TC
6
1
The bits in these registers are set by various conditions in the SCI
hardware and are automatically cleared by special acknowledge
sequences. The receive related flag bits in SCxSR1 (RDRF, IDLE, OR,
NF, FE, and PF) are all cleared by a read of the SCxSR1 register
followed by a read of the transmit/receive data register low byte.
However, only those bits which were set when SCxSR1 was read will be
cleared by the subsequent read of the transmit/receive data register low
byte. The transmit related bits in SCxSR1 (TDRE and TC) are cleared by
a read of the SCxSR1 register followed by a write to the transmit/receive
data registerl low byte.
Read anytime (used in auto clearing mechanism). Write has no meaning
or effect.
TDRE — Transmit Data Register Empty Flag
TC — Transmit Complete Flag
New data will not be transmitted unless SCxSR1 is read before writing
to the transmit data register. Reset sets this bit.
Flag is set when the transmitter is idle (no data, preamble, or break
transmission in progress). Clear by reading SCxSR1 with TC set and
then writing to SCxDR.
0 = SCxDR busy
1 = Any byte in the transmit data register is transferred to the serial
0 = Transmitter busy
1 = Transmitter is idle
RDRF
5
0
shift register so new data may now be written to the transmit
data register.
Multiple Serial Interface
IDLE
4
0
OR
3
0
NF
2
0
MC68HC912D60A — Rev. 3.1
FE
1
0
Freescale Semiconductor
Bit 0
PF
0
$00C4/$00CC