MC68HC711P2CFN4 Freescale Semiconductor, MC68HC711P2CFN4 Datasheet - Page 85

• Manufacturer Part Number: MC68HC711P2CFN4
• Description: IC MCU 32K OTP 4MHZ 84-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711P2CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: MI Bus, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.12.2 CONFIG — System configuration register
MC68HC11P2 — Rev 1.0
Configuration control (CONFIG) $003F ROMAD
CWOM — Port C wired-OR mode
STRCH — Stretch external accesses (refer to
On-Chip
IRVNE — Internal read visibility/not E (refer to
On-Chip
LSBF — LSB first enable (refer to
SPR2 — SPI clock rate select (refer to
(SPI))
Bits 1, 0 — not implemented; always read zero.
ROMAD — ROM mapping control (refer to
Chip
Freescale Semiconductor, Inc.
In single chip mode this bit determines whether the E clock drives
out from the chip.
Address bit 7
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1 = Port C outputs are open-drain.
0 = Port C operates normally.
1 = Off-chip accesses are extended by one E clock cycle.
0 = Normal operation.
1 = Data from internal reads is driven out of the external data bus.
0 = No visibility of internal reads on external bus.
1 = E pin is driven low.
0 = E clock is driven out from the chip.
1 = Data is transferred LSB first.
0 = Data is transferred MSB first.
1 = ROM addressed from $8000 to $FFFF.
0 = ROM addressed from $0000 to $7FFF (expanded mode only).
Memory)
Memory)
Memory)
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Parallel Input/Output
bit 6
1
bit 5
1
PARENNOSECNOCOPROMON EEON x11x 1xxx
bit 4
Serial Peripheral Interface
bit 3
Serial Peripheral Interface
Operating Modes and On-
bit 2
Operating Modes and
Operating Modes and
bit 1
System configuration
Parallel Input/Output
bit 0
Technical Data
(SPI))
on reset
State