C8051F352 Silicon Laboratories Inc, C8051F352 Datasheet - Page 24
C8051F352
Manufacturer Part Number
C8051F352
Description
IC 8051 MCU 8K FLASH 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F35xr
Specifications of C8051F352
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x16b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
C8051F35x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit
On-chip Dac
8 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F352
Manufacturer:
SILICON
Quantity:
364
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Manufacturer:
Silicon Laboratories Inc
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Silicon Laboratories Inc
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Silicon Laboratories Inc
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C8051F352R
Manufacturer:
Silicon Laboratories Inc
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C8051F350/1/2/3
1.6.
C8051F350/1/2/3 devices include a software-configurable voltage comparator with an input multiplexer.
The Comparator offers programmable response time and hysteresis and two outputs that are optionally
available at the Port pins: a synchronous “latched” output (CP0), or an asynchronous “raw” output (CP0A).
Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these inter-
rupts may be used as a “wake-up” source for the processor. Comparator0 may also be configured as a
reset source. A block diagram of the Comparator is shown in Figure 1.9.
1.7.
The C8051F350/1/2/3 Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud
rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hard-
ware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.
24
Port I/O
Pins
Programmable Comparator
Serial Ports
Figure 1.9. Comparator0 Block Diagram
+
-
GND
VDD
Decision
Reset
Tree
Rev. 0.4
(SYNCHRONIZER)
D
SET
CLR
Q
Q
D
CLR
SET
Interrupt
Q
Q
Logic
(asynchronous output)
(synchronous output)
CP0A
CP0