C8051F331 Silicon Laboratories Inc, C8051F331 Datasheet - Page 9

• Manufacturer Part Number: C8051F331
• Description: IC 8051 MCU 8K FLASH 20MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F33xr

Specifications of C8051F331

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

11. Flash Memory
12. External RAM
13. Oscillators
14. Port Input/Output
15. SMBus
Figure 10.3. VDM0CN: VDD Monitor Control ........................................................... 91
Figure 10.4. RSTSRC: Reset Source Register ........................................................ 93
Table 10.1. Reset Electrical Characteristics............................................................. 94
Table 11.1. Flash Electrical Characteristics ............................................................. 96
Figure 11.1. Flash Program Memory Map................................................................ 97
Figure 11.2. PSCTL: Program Store R/W Control.................................................... 99
Figure 11.3. FLKEY: Flash Lock and Key Register .................................................. 99
Figure 11.4. FLSCL: Flash Scale Register ............................................................. 100
Figure 12.1. EMI0CN: External Memory Interface Control ..................................... 101
Figure 13.1. Oscillator Diagram.............................................................................. 103
Figure 13.2. OSCICL: Internal H-F Oscillator Calibration Register ........................ 104
Figure 13.3. OSCICN: Internal H-F Oscillator Control Register ............................. 104
Figure 13.4. OSCLCN: Internal L-F Oscillator Control Register ............................. 105
Figure 13.5. OSCXCN: External Oscillator Control Register.................................. 107
Figure 13.6. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram . 109
Figure 13.7. CLKSEL: Clock Select Register ......................................................... 111
Table 13.1. Internal Oscillator Electrical Characteristics ........................................ 112
Figure 14.1. Port I/O Functional Block Diagram ..................................................... 113
Figure 14.2. Port I/O Cell Block Diagram ............................................................... 114
Figure 14.3. Crossbar Priority Decoder with No Pins Skipped ............................... 115
Figure 14.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 116
Figure 14.5. XBR0: Port I/O Crossbar Register 0................................................... 118
Figure 14.6. XBR1: Port I/O Crossbar Register 1................................................... 119
Figure 14.7. P0: Port0 Register .............................................................................. 120
Figure 14.8. P0MDIN: Port0 Input Mode Register.................................................. 120
Figure 14.9. P0MDOUT: Port0 Output Mode Register ........................................... 121
Figure 14.10. P0SKIP: Port0 Skip Register............................................................ 121
Figure 14.11. P1: Port1 Register ............................................................................ 121
Figure 14.12. P1MDIN: Port1 Input Mode Register................................................ 122
Figure 14.13. P1MDOUT: Port1 Output Mode Register ......................................... 122
Figure 14.14. P1SKIP: Port1 Skip Register............................................................ 122
Figure 14.15. P2: Port2 Register ............................................................................ 123
Figure 14.16. P2MDOUT: Port2 Output Mode Register ......................................... 123
Table 14.1. Port I/O DC Electrical Characteristics.................................................. 124
Figure 15.1. SMBus Block Diagram ....................................................................... 125
Figure 15.2. Typical SMBus Configuration ............................................................. 126
Figure 15.3. SMBus Transaction ............................................................................ 127
Table 15.1. SMBus Clock Source Selection........................................................... 130
Figure 15.4. Typical SMBus SCL Generation......................................................... 131
Table 15.2. Minimum SDA Setup and Hold Times ................................................. 131
C8051F330/1, C8051F330D
Rev. 1.2
9