C8051F331 Silicon Laboratories Inc, C8051F331 Datasheet - Page 184

• Manufacturer Part Number: C8051F331
• Description: IC 8051 MCU 8K FLASH 20MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F33xr

Specifications of C8051F331

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

C8051F330/1, C8051F330D
18.3.2. 8-bit Timers with Auto-Reload
When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TH3 and TL3). Both 8-bit timers operate in
auto-reload mode as shown in Figure 18.12. TMR3RLL holds the reload value for TL3; TMR3RLH holds
the reload value for TH3. The TR3 bit in TMR3CN handles the run control for TH3. TL3 is always running
when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock
source divided by 8. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON) select either SYSCLK or
the clock defined by the Timer 3 External Clock Select bit (T3XCLK in TMR3CN), as follows:
The TF3H bit is set when TH3 overflows from 0xFF to 0x00; the TF3L bit is set when TL3 overflows from
0xFF to 0x00. When Timer 3 interrupts are enabled (IE.5), an interrupt is generated each time TH3 over-
flows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each
time either TL3 or TH3 overflows. When TF3LEN is enabled, software must check the TF3H and TF3L
flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not cleared
by hardware and must be manually cleared by software.
184
External Clock / 8
T3MH
0
0
1
SYSCLK / 12
T3XCLK
T3XCLK
X
0
1
0
1
SYSCLK / 12
External Clock / 8
SYSCLK
SYSCLK
Figure 18.19. Timer 3 8-Bit Mode Block Diagram
TH3 Clock
Source
0
1
1
0
T
3
M
H
M
T
3
L
CKCON
M
H
T
2
M
T
2
L
TR3
M
T
1
M
T
0
S
C
A
1
S
C
A
0
Rev. 1.2
TCLK
TCLK
TMR3RLH
TMR3RLL
TH3
TL3
T3ML
Reload
Reload
0
0
1
T3XCLK
To ADC
T3SPLIT
TF3LEN
TF3CEN
T3XCLK
TF3H
X
TF3L
0
1
TR3
TL3 Clock Source
SYSCLK / 12
External Clock / 8
SYSCLK
Interrupt