C8051F017 Silicon Laboratories Inc, C8051F017 Datasheet - Page 161

• Manufacturer Part Number: C8051F017
• Description: IC 8051 MCU 32K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F01xr

Specifications of C8051F017

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 4x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• On-chip Dac: 12 bit, 2 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

161
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Bit7:
Bits6-3: UNUSED. Read = 0000b, Write = don’t care.
Bits2-1: CPS1-CPS0: PCA Counter/Timer Pulse Select.
Bit0:
CIDL
R/W
Bit7
CIDL: PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
These bits select the timebase source for the PCA counter.
ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.
CPS1
0
0
1
1
R/W
Bit6
-
CPS0
0
1
0
1
Figure 20.9. PCA0MD: PCA Mode Register
R/W
Bit5
-
Timebase
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock divided by 4)
R/W
Bit4
-
Rev. 1.7
R/W
Bit3
-
CPS1
R/W
Bit2
CPS0
R/W
Bit1
ECF
R/W
Bit0
SFR Address:
Reset Value
00000000
0xD9