C8051F022 Silicon Laboratories Inc, C8051F022 Datasheet - Page 101
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C8051F022
Manufacturer Part Number
C8051F022
Description
IC 8051 MCU 64K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Specifications of C8051F022
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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12.
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™
instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has
a superset of all the peripherals included with a standard 8051. Included are five 16-bit counter/timers (see descrip-
tion in
RAM, 128 byte Special Function Register (SFR) address space (see
description in
interfaces directly with the MCUs' analog and digital subsystems providing a complete data acquisition or control-
system solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional
custom peripherals and functions to extend its capability (see Figure 12.1 for a block diagram). The CIP-51 includes
the following features:
-
-
-
-
-
Fully Compatible with MCS-51 Instruction Set
25 MIPS Peak Throughput with 25 MHz Clock
0 to 25 MHz Clock Frequency
256 Bytes of Internal RAM
8/4 Byte-Wide I/O Ports
Section
CIP-51 MICROCONTROLLER
Section
22), two full-duplex UARTs (see description in
17). The CIP-51 also includes on-chip debug hardware (see description in
RESET
CLOCK
STOP
IDLE
ACCUMULATOR
PROGRAM COUNTER (PC)
CONTROL
PSW
PRGM. ADDRESS REG.
LOGIC
POWER CONTROL
PC INCREMENTER
Figure 12.1. CIP-51 Block Diagram
DATA POINTER
REGISTER
BUFFER
TMP1
PIPELINE
ALU
TMP2
DATA BUS
DATA BUS
D8
D8
D8
Rev. 1.4
-
-
-
-
-
A16
D8
D8
D8
D8
B REGISTER
Extended Interrupt Handler
Reset Input
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security
Section 20
REGISTER
INTERRUPT
Section
ADDRESS
INTERFACE
INTERFACE
INTERFACE
MEMORY
SRAM
SFR
BUS
12.2.6), and 8/4 byte-wide I/O Ports (see
and
MEM_WRITE_DATA
SFR_WRITE_DATA
MEM_READ_DATA
STACK POINTER
(256 X 8)
SFR_READ_DATA
C8051F020/1/2/3
SRAM
MEM_CONTROL
EMULATION_IRQ
MEM_ADDRESS
SFR_CONTROL
SFR_ADDRESS
Section
SYSTEM_IRQs
21), 256 bytes of internal
Section
24), and
101