C8051F005 Silicon Laboratories Inc, C8051F005 Datasheet - Page 135

• Manufacturer Part Number: C8051F005
• Description: IC 8051 MCU 32K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F00xr

Specifications of C8051F005

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

18.2.
Modes 2 and 3 support multiprocessor communication between a master processor and one or more slave processors
by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it first sends
an address byte to select the target(s). An address byte differs from a data byte in that its ninth bit is logic 1; in a
data byte, the ninth bit is always set to logic 0.
Setting the SM2 bit (SCON.5) of a slave processor configures its UART such that when a stop bit is received, the
UART will generate an interrupt only if the ninth bit is logic one (RB8 = 1) signifying an address byte has been
received. In the UART’s interrupt handler, software will compare the received address with the slave’s own
assigned 8-bit address. If the addresses match, the slave will clear its SM2 bit to enable interrupts on the reception
of the following data byte(s). Slaves that weren’t addressed leave their SM2 bits set and do not generate interrupts
on the reception of the following data bytes, thereby ignoring the data. Once the entire message is received, the
addressed slave resets its SM2 bit to ignore all transmissions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple slaves,
thereby enabling “broadcast” transmissions to more than one slave simultaneously. The master processor can be
configured to receive all transmissions or a protocol can be implemented such that the master/slave role is
temporarily reversed to enable half-duplex transmission between the original master and slave(s).
135
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
RX
Master
Device
Multiprocessor Communications
TX
Figure 18.7. UART Multi-Processor Mode Interconnect Diagram
RX
Device
Slave
TX
Rev. 1.7
RX
Device
Slave
TX
RX
Device
Slave
TX
VDD