MC68HC908JB12JDW Freescale Semiconductor, MC68HC908JB12JDW Datasheet - Page 129

• Manufacturer Part Number: MC68HC908JB12JDW
• Description: IC MCU 12K FLASH 6MHZ USB 20SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JB12JDW

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: SCI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

9.4.2 Data Format
9.4.3 Break Signal
9.4.4 Baud Rate
MC68HC908JB16
Freescale Semiconductor
—
Rev. 1.1
Communication with the monitor ROM is in standard non-return-to-zero
(NRZ) mark/space data format. Transmit and receive baud rates must
be identical.
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When
the monitor receives a break signal, it drives the PTA0 pin high for the
duration of two bits and then echoes back the break signal.
The communication baud rate is dependant on oscillator frequency,
f
is by IRQ = V
PTA3 pin is at logic zero upon entry into monitor mode, the divide by ratio
is 312.
XCLK
Blank reset vector,
START
Monitor Mode
BIT
. The state of PTA3 also affects baud rate if entry to monitor mode
IRQ = V
IRQ = V
Entry By:
0
BIT 0
1
TST
DD
TST
2
MISSING STOP BIT
Table 9-3. Monitor Baud Rate Selection
Monitor ROM (MON)
BIT 1
. When PTA3 is high, the divide by ratio is 625. If the
3
Figure 9-3. Monitor Data Format
Figure 9-4. Break Transaction
4
BIT 2
Oscillator Clock
5
Frequency,
6
12 MHz
12 MHz
12 MHz
BIT 3
f
CLK
7
BIT 4
BIT 5
TWO-STOP-BIT DELAY BEFORE ZERO ECHO
PTA3
X
0
1
BIT 6
0
1
BIT 7
2
3
Monitor ROM (MON)
STOP
Baud Rate
BIT
38400 bps
19200 bps
19200 bps
4
Technical Data
START
NEXT
5
BIT
6
7
129