MC68HC908GZ8MFJ Freescale Semiconductor, MC68HC908GZ8MFJ Datasheet - Page 55

• Manufacturer Part Number: MC68HC908GZ8MFJ
• Description: IC MCU 8K FLASH 8MHZ CAN 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GZ8MFJ

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

3.8.2 ADC Data Register High and Data Register Low
3.8.2.1 Left Justified Mode
In left justified mode, the ADRH register holds the eight MSBs of the 10-bit result. The only difference from
left justified mode is that the AD9 is complemented. The ADRL register holds the two LSBs of the 10-bit
result. All other bits read as 0. ADRH and ADRL are updated each time an ADC single channel conversion
completes. Reading ADRH latches the contents of ADRL until ADRL is read. All subsequent results will
be lost until the ADRH and ADRL reads are completed.
3.8.2.2 Right Justified Mode
In right justified mode, the ADRH register holds the two MSBs of the 10-bit result. All other bits read as 0.
The ADRL register holds the eight LSBs of the 10-bit result. ADRH and ADRL are updated each time an
ADC single channel conversion completes. Reading ADRH latches the contents of ADRL until ADRL is
read. All subsequent results will be lost until the ADRH and ADRL reads are completed.
Freescale Semiconductor
Address:
Address:
Address:
Address:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Figure 3-5. ADC Data Register High (ADRH) and Low (ADRL)
Figure 3-6. ADC Data Register High (ADRH) and Low (ADRL)
$003D
$003E
$003D
$003E
Bit 7
AD9
AD1
Bit 7
AD7
0
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
= Unimplemented
= Unimplemented
AD8
AD0
AD6
6
6
0
AD7
AD5
5
0
5
0
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
AD6
AD4
4
0
4
0
AD5
AD3
3
0
3
0
AD4
AD2
2
0
2
0
AD3
AD9
AD1
1
0
1
ADRH
ADRH
ADRL
ADRL
Bit 0
AD2
Bit 0
AD8
AD0
0
I/O Registers
55