MC908AS60ACFN Freescale Semiconductor, MC908AS60ACFN Datasheet - Page 220

• Manufacturer Part Number: MC908AS60ACFN
• Description: IC MCU 60K FLASH 8.4MHZ 52PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AS60ACFN

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Serial Peripheral Interface (SPI)
When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data
direction register of the shared I/O port.
19.12.4 SS (Slave Select)
The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a
slave, the SS is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission.
19.5 Transmission Formats
high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low
throughout the transmission for the CPHA = 1 format. See
When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as
a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can
still prevent the state of the SS from creating a MODF error. (See
Register).
When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to
prevent multiple masters from driving MOSI and SPSCK. (See
the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN bit
is low for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data
direction register of the shared I/O port. With MODFEN high, it is an input-only pin to the SPI regardless
of the state of the data direction register of the shared I/O port.
The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and
reading the data register. (See
220
X = don’t care
SPE
MASTER SS
MISO/MOSI
A high voltage on the SS pin of a slave SPI puts the MISO pin in a
high-impedance state. The slave SPI ignores all incoming SPSCK clocks,
even if a transmission already has begun.
0
1
1
1
SLAVE SS
SLAVE SS
CPHA = 0
CPHA = 1
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
SPMSTR
X
0
1
1
Since it is used to indicate the start of a transmission, the SS must be toggled
MODFEN
Table
X
X
0
1
BYTE 1
Figure 19-11. CPHA/SS Timing
Table 19-4. SPI Configuration
19-4).
Master without MODF
SPI Configuration
Master with MODF
Not Enabled
Slave
NOTE
BYTE 2
Figure
19.6.2 Mode Fault
19-11.
19.13.2 SPI Status and Control
General-Purpose I/O;
General-Purpose I/O;
State of SS Logic
SS Ignored by SPI
SS Ignored by SPI
Input-Only to SPI
Input-Only to SPI
BYTE 3
Error). For the state of
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