COP8SCR9IMT7 National Semiconductor, COP8SCR9IMT7 Datasheet - Page 26
![IC MCU EEPROM 8BIT 32K 48-TSSOP](/photos/6/64/66474/14-48-tssop_sml.jpg)
COP8SCR9IMT7
Manufacturer Part Number
COP8SCR9IMT7
Description
IC MCU EEPROM 8BIT 32K 48-TSSOP
Manufacturer
National Semiconductor
Series
COP8™ 8Sr
Datasheet
1.COP8SCR9HVA8NOPB.pdf
(80 pages)
Specifications of COP8SCR9IMT7
Core Processor
COP8
Core Size
8-Bit
Speed
20MHz
Connectivity
Microwire/Plus (SPI), UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
*COP8SCR9IMT7
www.national.com
10.0 Functional Description
10.9.5 T3CNTRL Register (Address X'00B6)
The T3CNTRL register contains the following bits:
Bit 7
(Continued)
T3C3
T3C3
T3C2
T3C1
T3C0
T3PNDA Timer T3 Interrupt Pending Flag (Autoreload
T3ENA
T3PNDB Timer T3 Interrupt Pending Flag for T3B cap-
T3ENB
T3C2
Timer T3 mode control bit
Timer T3 mode control bit
Timer T3 mode control bit
Timer
modes 1 and 2, Timer T3 Underflow Interrupt
Pending Flag in timer mode 3
RA in mode 1, T3 Underflow in mode 2, T3A
capture edge in mode 3)
Timer T3 Interrupt Enable for Timer Underflow
or T3A Input capture edge
ture edge
Timer T3 Interrupt Enable for T3B Input capture
edge
T3C1
T3
T3C0
Start/Stop
T3PNDA
T3ENA
control
T3PNDB
in
T3ENB
timer
Bit 0
26
10.9.6 HSTCR Register (Address X'00AF)
The HSTCR register contains the following bits:
10.9.7 ITMR Register (Address X'00CF)
The ITMR register contains the following bits:
Bit 7
Bit 7
LSON
T3HS Places Timer T3 in High Speed Mode.
T2HS Places Timer T2 in High Speed Mode.
LSON
HSON
DCEN
CCKSEL Selects the high speed oscillator or the low
RSVD
ITSEL2
ITSEL1
ITSEL0
HSON
Turns the low speed oscillator on or off.
Turns the high speed oscillator on or off.
Selects the high speed oscillator or the low
speed oscillator as the Idle Timer Clock.
speed oscillator as the primary CPU clock.
This bit is reserved and must be 0.
Idle Timer period select bit.
Idle Timer period select bit.
Idle Timer period select bit.
DCEN
Reserved
CCKS
EL
RSVD
ITSEL2
ITSEL1
T3HS
ITSEL0
T2HS
Bit 0
Bit 0