MC68HC908GT8CFB Freescale Semiconductor, MC68HC908GT8CFB Datasheet - Page 135

• Manufacturer Part Number: MC68HC908GT8CFB
• Description: IC MCU 8K FLASH 8MHZ 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GT8CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 34
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

12.6.1 Port E Data Register
The port E data register contains a data latch for each of the five port E pins.
PTE4-PTE0 — Port E Data Bits
OSC2 and OSC1 — OSC2 and OSC1 Bits
RxD — SCI Receive Data Input
TxD — SCI Transmit Data Output
12.6.2 Data Direction Register E
Data direction register E (DDRE) determines whether each port E pin is an input or an output. Writing a 1
to a DDRE bit enables the output buffer for the corresponding port E pin; a 0 disables the output buffer.
Freescale Semiconductor
These read/write bits are software-programmable. Data direction of each port E pin is under the control
of the corresponding bit in data direction register E. Reset has no effect on port Edata.
Under software control, PTE4 and PTE3 can be configured as external clock inputs and outputs. PTE3
will become an output clock, OSC2, if selected in the configuration registers and enabled in the ICG
registers. PTE4 will become an external input clock source, OSC1, if selected in the configuration
registers and enabled in the ICG registers. See
Chapter 5 Computer Operating Properly (COP)
have no effect and reads return undefined values.
The PTE1/RxD pin is the receive data input for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. See
Chapter 14 Enhanced Serial Communications Interface (ESCI)
The PTE0/TxD pin is the transmit data output for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. See
Chapter 14 Enhanced Serial Communications Interface (ESCI)
Alternative Function:
Data direction register E (DDRE) does not affect the data direction of port
E pins that are being used by the SCI module. However, the DDRE bits
always determine whether reading port E returns the states of the latches
or the states of the pins. See
Address:
Reset:
Read:
Write:
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
$0008
Bit 7
0
Figure 12-17. Port E Data Register (PTE)
= Unimplemented
6
0
Table
5
0
NOTE
Chapter 7 Internal Clock Generator (ICG) Module)
12-6.
Module. While configured as oscillator pins, writes
Unaffected by reset
OSC1
PTE4
4
OSC2
PTE3
3
Module.
Module.
PTE2
2
PTE1
RxD
1
PTE0
Bit 0
TxD
Port E
and
135