MC68HC908GT8CFB Freescale Semiconductor, MC68HC908GT8CFB Datasheet - Page 100

• Manufacturer Part Number: MC68HC908GT8CFB
• Description: IC MCU 8K FLASH 8MHZ 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GT8CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 34
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Internal Clock Generator (ICG) Module)
7.7.3 ICG Trim Register
TRIM7:TRIM0 — ICG Trim Factor Bits
7.7.4 ICG DCO Divider Register
DDIV3:DDIV0 — ICG DCO Divider Control Bits
7.7.5 ICG DCO Stage Register
DSTG7:DSTG0 — ICG DCO Stage Control Bits
100
These read/write bits change the size of the internal capacitor used by the internal clock generator. By
testing the frequency of the internal clock and incrementing or decrementing this factor accordingly,
the accuracy of the internal clock can be improved to ± 2 percent. Incrementing this register by one
decreases the frequency by 0.195 percent of the unadjusted value. Decrementing this register by one
increases the frequency by 0.195 percent. This register cannot be written when the CMON bit is set.
Reset sets these bits to $80, centering the range of possible adjustment.
These bits indicate the number of divide-by-twos (DDIV) that follow the digitally controlled oscillator.
When ICGON is set, DDIV is controlled by the digital loop filter. The range of valid values for DDIV is
from $0 to $9. Values of $A through $F are interpreted the same as $9. Since the DCO is active during
reset, reset has no effect on DSTG and the value may vary.
These bits indicate the number of stages (above the minimum) in the digitally controlled oscillator. The
total number of stages is approximately equal to $1FF, so changing DSTG from $00 to $FF will
approximately double the period. Incrementing DSTG will increase the period (decrease the
frequency) by 0.202 percent to 0.368 percent (decrementing has the opposite effect). DSTG cannot
be written when ICGON is set to prevent inadvertent frequency shifting. When ICGON is set, DSTG is
controlled by the digital loop filter. Since the DCO is active during reset, reset has no effect on DSTG
and the value may vary.
Address: $0038
Address: $0039
Address: $003A
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
DSTG7
Figure 7-15. ICG DCO Divider Control Register (ICGDVR)
TRIM7
Figure 7-16. ICG DCO Stage Control Register (ICGDSR)
Bit 7
Bit 7
Bit 7
R
R
1
0
= Unimplemented
= Reserved
DSTG6
TRIM6
Figure 7-14. ICG Trim Register (ICGTR)
R
0
6
6
0
6
DSTG5
TRIM5
R
5
0
5
0
5
DSTG4
TRIM4
Unaffected by reset
R
4
0
4
0
4
U = Unaffected
DSTG3
TRIM3
DDIV3
U
R
3
0
3
3
DSTG2
TRIM2
DDIV2
U
R
2
0
2
2
DSTG1
TRIM1
DDIV1
U
R
1
0
1
1
Freescale Semiconductor
DSTG0
TRIM0
DDIV0
Bit 0
Bit 0
Bit 0
U
R
0