MCF5307FT66B Freescale Semiconductor, MCF5307FT66B Datasheet - Page 472
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MCF5307FT66B
Manufacturer Part Number
MCF5307FT66B
Description
IC MPU 32BIT COLDF 66MHZ 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307FT66B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Glossary-14
N
S
O
P
Nop. No-operation. A single-cycle operation that does not affect registers or
Overflow. An condition that occurs during arithmetic operations when the
Pipelining. A technique that breaks operations, such as instruction
Precise mode. A memory access mode that ensures that all write accesses to
Set (v) To write a nonzero value to a bit or bit field; the opposite of clear. The
Set (n). A subdivision of a cache. Cacheable data can be stored in a given
Set-associativity. Aspect of cache organization in which the cache space is
Slave. The device addressed by a master device. The slave is identified in the
Static branch prediction. Mechanism by which software (for example,
Supervisor mode. The privileged operation state of a processor. In
generate bus activity.
result cannot be stored accurately in the destination register(s). For
example, if two 16-bit numbers are multiplied, the result may not be
representable in 16 bits.
processing or bus transactions, into smaller distinct stages or tenures
(respectively) so that a subsequent operation can begin before the
previous one completes.
a specified memory region occur in order.
term ‘set’ may also be used to generally describe the updating of a
bit or bit field.
location in any one of the sets, typically corresponding to its lower-
order address bits. Because several memory locations can map to the
same location, cached data is typically placed in the set whose cache
line corresponding to that address was used least recently. See Set-
associativity.
divided into sections, called sets. The cache controller associates a
particular main memory address with the contents of a particular set,
or region, within the cache.
address tenure and is responsible for supplying or latching the
requested data for the master during the data tenure.
compilers) can hint to the machine hardware about the direction a
branch is likely to take.
supervisor mode, software, typically the operating system, can
access all control registers and can access the supervisor memory
space, among other privileged operations.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MCF5307 User’s Manual
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