MCF5307FT66B Freescale Semiconductor, MCF5307FT66B Datasheet - Page 184
MCF5307FT66B
Manufacturer Part Number
MCF5307FT66B
Description
IC MPU 32BIT COLDF 66MHZ 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307FT66B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Programming Model
6.2.2 Module Base Address Register (MBAR)
The supervisor-level MBAR, Figure 6-2, specifies the base address and allowable access
types for all internal peripherals. It is written with a MOVEC instruction using the CPU
address 0xC0F. (See the ColdFire Family Programmer’s Reference Manual.) MBAR can
be read or written through the debug module as a read/write register, as described in
Chapter 5, “Debug Support.” Only the debug module can read MBAR.
The valid bit, MBAR[V], is cleared at system reset to prevent incorrect references before
MBAR is written; other MBAR bits are uninitialized at reset. To access internal peripherals,
write MBAR with the appropriate base address (BA) and set MBAR[V] after system reset.
All internal peripheral registers occupy a single relocatable memory block along 4-Kbyte
boundaries. If MBAR[V] is set, MBAR[BA] is compared to the upper 20 bits of the full
32-bit internal address to determine if an internal peripheral is being accessed. MBAR
masks specific address spaces using the address space fields. Attempts to access a masked
address space generate an external bus access.
Addresses hitting overlapping memory spaces take the following priority:
6-4
Address
MBAR
Offset
0x04C
0x050
0x054
Reset
Field
1. MBAR
2. SRAM and caches
3. Chip select
R/W
31
UART0 (ICR4) [p. 9-3]
DMA2 (ICR8) [p. 9-3]
timer (ICR0) [p. 9-3]
Software watchdog
The MBAR region must be mapped to non-cacheable space.
W (supervisor only); R/W through debug module (only the debug module can read MBAR)
[31:24]
Figure 6-2. Module Base Address Register (MBAR)
Freescale Semiconductor, Inc.
Table 6-1. SIM Registers (Continued)
For More Information On This Product,
BA
Timer0 (ICR1) [p. 9-3]
UART1 (ICR5) [p. 9-3]
DMA3 (ICR9) [p. 9-3]
Go to: www.freescale.com
MCF5307 User’s Manual
[23:16]
NOTE:
CPU + 0x0C0F
Undefined
12 11 10 9
Timer1 (ICR2) [p. 9-3]
DMA0 (ICR6) [p. 9-3]
—
[15:8]
WP — AM C/I SC SD UC UD V
8
7
Reserved
Attribute Mask Bits
6
DMA1 (ICR7) [p. 9-3]
5
I
2
C (ICR3) [p. 9-3]
4
[7:0]
3
2
1
0
0
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