COP8CDR9IMT8 National Semiconductor, COP8CDR9IMT8 Datasheet - Page 53

• Manufacturer Part Number: COP8CDR9IMT8
• Description: IC MCU CMOS 8BIT 48-TSSOP
• Manufacturer: National Semiconductor
• Series: COP8™ 8Cr

Specifications of COP8CDR9IMT8

• Core Processor: COP8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: Microwire/Plus (SPI), UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: *COP8CDR9IMT8

15.0 A/D Converter
Note 18: This Input Channel Selection should not be used when the Multiplexor Output is enabled.
Note 19: This Input Channel Selection should not be used in Differential Mode when the Multiplexor Output is enabled.
15.1.1.2 Multiplexor Output Select
This 1-bit field allows the output of the A/D multiplexor and
the input to the A/D to be connected directly to external pins.
This allows for an external, common filter/signal conditioning
circuit to be applied to all channels. The output of the exter-
nal conditioning circuit can then be connected directly to the
input of the Sample and Hold input on the A/D Converter.
See Figure 26 for the single ended mode diagram. The
Multiplexor output is connected to ADCH14 and the A/D
input is connected to ADCH15. For Differential mode, the
differential multiplexor outputs are available and should be
converted to a single ended voltage for connection to the A/D
Converter Input. See Figure 27.
The channel assignments for this mode are shown in Table
22.
When using the Mux Output feature, the delay though the
internal multiplexor to the pin, plus the delay of the external
filter circuit, plus the internal delay to the Sample and Hold
will exceed the three clock cycles that’s allowed in the con-
version. This adds the requirement that, whenever the MUX
bit = 1, that the channel selected by ADCH3:0 bits be en-
abled, even when ADBSY = 0, and gated to the mux output
pin. The input path to the A/D converter is also enabled. This
ADCH3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
TABLE 21. A/D Converter Channel Selection when the Multiplexor Output is Enabled
ADCH2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Select Bits
(Continued)
ADCH1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ADCH0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
53
allows the input channel to be selected and settled before
starting a conversion. The sequence to perform conversions
using the Mux Out feature is a multistep process and is listed
below.
1. Select the desired channel and operating modes and
2. Wait the appropriate time until the analog input has
3. Select the same desired channel and operating modes
4. Poll ADBSY until it is cleared by the hardware. This
5. Obtain the results from the result registers.
The port pins used for the multiplexor output must be con-
figured as high impedance inputs. If the port pins are con-
figured as outputs, or as inputs with weak pull-up, there will
be a conflict between the analog signal output and the
digitally driven output.
load them into ENAD without setting ADBSY.
settled. This will depend on the application and the
response of the external circuit.
used in step 1 and load them into ENAD and also set
ADBSY or set ADBSY by using the SBIT instruction.
This will start the conversion.
indicates the completion of the conversion.
A/D Input (Note
Single Ended
Mode Select
Channel No.
ADMOD = 0
Mux Output
ADCH14 is
ADCH15 is
(Note 18)
Mode
18)
10
12
13
11
0
1
2
3
4
5
6
7
8
9
Not Used (Note
A/D Input (Note
Channel Pairs
Mux Output −
Mux Output +
Mode Select
ADMOD = 1
Differential
ADCH14 is
ADCH15 is
ADC13 is
(Note 19)
(Note 18)
10, 11
11, 10
Mode
(+, −)
0, 1
1, 0
2, 3
3, 2
4, 5
5, 4
6, 7
7, 6
8, 9
9, 8
19)
18)
Mux Output
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Enabled
MUX
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1