MC68HC711K4CFU4 Freescale Semiconductor, MC68HC711K4CFU4 Datasheet - Page 32

• Manufacturer Part Number: MC68HC711K4CFU4
• Description: IC MCU 24K 4MHZ EEPROM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711K4CFU4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.3.3 General-Purpose Chip Selects (CSGP1, CSGP2)
4.3.4 Chip Select Priorities
4.3.5 Chip Select Control Registers
CSCTL — Chip Select Control
IOEN —I/O Chip Select Enable
IOPL —I/O Chip Select Polarity Select
32
MOTOROLA
RESET:
The general-purpose chip selects are the most flexible and programmable and have the most control
bits. Polarity of active state, E valid or address valid, size, and starting address are all programmable.
Clock stretching can be set from zero to three cycles. Each chip select can be programmed to become
active whenever the CPU address enters a memory expansion window regardless of the actual bank
selected. This is known as following a window.
Each general purpose chip select can be configured to drive the program chip select. CSGP1 can be
configured to drive CSGP2 or the program chip select. Using one chip select to drive another allows the
same device to cover the address space defined by both chip selects. The two chip selects are con-
nected to an internal OR gate. The output of the OR gate is then driven onto the pin corresponding to
the driven chip select. For example, this is useful when the same external device is used with both bank
windows but the windows are opened independently. In cases where one chip select drives another,
determine the priority from the following table.
To minimize chip select conflicts (with one another or with internal memory and registers), the priority
is determined by the GCSPR bit in the CSCTL register. Refer to the following table.
There are six chip select control registers. Chip select functions are enabled by control bits in CSCTL
register. Chip selects are configured by bits in CSCSTR, IOEN, IOPL, IOCSA, and IOSZ registers.
0 = CSIO disabled
1 = CSIO enabled
0 = CSIO active low
1 = CSIO active high
IOEN
Bit 7
0
GPCS1 and GPCS2 drive PCS
IOPL
On-Chip ROM/EPROM
6
0
GPCS1 drives GPCS2
Program Chip Select
Freescale Semiconductor, Inc.
GPCS1 drives PCS
GPCS2 drives PCS
On-Chip EEPROM
On-Chip Registers
GP Chip Select 1
GP Chip Select 2
Bootloader ROM
I/O Chip Select
On-Chip RAM
For More Information On This Product,
GCSPR = 0
Condition
IOCSA
5
0
Go to: www.freescale.com
IOSZ
4
0
GCSPR
3
0
On-Chip ROM/EPROM
Program Chip Select
On-Chip EEPROM
On-Chip Registers
GP Chip Select 1
GP Chip Select 2
Bootloader ROM
I/O Chip Select
On-Chip RAM
GCSPR = 1
PCSEN
Priority
GPCS1
GPCS1
GPCS2
GPCS1
2
1
PCSZA
1
0
PCSZB
M68HC11 K Series
$005B
MC68HC11KTS/D
Bit 0
0