MC68HC711K4CFU4 Freescale Semiconductor, MC68HC711K4CFU4 Datasheet - Page 25

• Manufacturer Part Number: MC68HC711K4CFU4
• Description: IC MCU 24K 4MHZ EEPROM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711K4CFU4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CONFIG —System Configuration Register
ROMAD —ROM/EPROM Mapping Control
Bit 6 —Not implemented
CLKX —XOUT Clock Enable
PAREN —Pull-Up Assignment Register Enable
NOSEC —Security Disable
NOCOP —COP System Disable
ROMON —ROM/EPROM Enable
EEON —EEPROM Enable
3.6 Security Feature
M68HC11 K Series
MC6HC11KTS/D
RESET:
In single-chip mode ROMAD is forced to one out of reset.
Always reads one
NOSEC is invalid unless the security mask option is specified before the MCU is manufactured. If se-
curity mask option is omitted NOSEC always reads one. Refer to 3.6 Security Feature.
Resets to programmed value
In single-chip mode, ROMON is forced to one out of reset. In special test mode, ROMON is forced to
zero out of reset.
The security feature protects memory contents from unauthorized access. Although many devices in
the M68HC11 family support the security feature, an enhancement has been added to the MC68S11K4
that protects the contents of EPROM/OTPROM.
The security feature affects how the MCU behaves in certain modes. When the optional security feature
has been specified prior to manufacture and enabled via the NOSEC bit in CONFIG, the MCU is re-
stricted to operation in single-chip modes only. When the NOSEC bit equals zero, the MCU ignores the
state of the MODA pin during reset. This allows the MCU to be operated in single-chip and bootstrap
modes only. These modes of operation do not allow external visibility of the internal address and data
buses. Although the security feature can easily be disabled when in bootstrap mode, the bootloader
firmware residing in bootstrap ROM checks to see if the NOSEC bit is clear. If NOSEC is clear (security
enabled), the bootloader program performs the following:
0 = ROM/EPROM located at $2000–$7FFF
1 = ROM/EPROM located at $A000–$FFFF
0 = XOUT pin disabled
1 = Buffered XTAL signal (four times E frequency) driven out on the XOUT pin
0 = Pull-ups always disabled regardless of state of bits in PPAR
1 = Pull-ups either enabled or disabled through PPAR
0 = Security enabled
1 = Security disabled
0 = COP enabled (forces reset on timeout)
1 = COP disabled (does not force reset on timeout)
0 = ROM/EPROM removed from memory map
1 = ROM/EPROM present in memory map
0 = EEPROM disabled from memory map
1 = EEPROM present in memory map with location depending on value specified in EE[3:0] in INIT2
ROMAD
Bit 7
—
6
1
1
Freescale Semiconductor, Inc.
For More Information On This Product,
CLKX
—
5
Go to: www.freescale.com
PAREN
—
4
NOSEC
—
3
NOCOP
—
2
ROMON
—
1
EEON
$003F
Bit 0
—
MOTOROLA
25