MC68HC16Z1CPV16 Freescale Semiconductor, MC68HC16Z1CPV16 Datasheet - Page 310
![IC MPU 1K RAM 16MHZ 144-LQFP](/photos/6/76/67683/375-144-tqfp_sml.jpg)
MC68HC16Z1CPV16
Manufacturer Part Number
MC68HC16Z1CPV16
Description
IC MPU 1K RAM 16MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HC16r
Datasheet
1.MC68HC16Z1VEH16.pdf
(500 pages)
Specifications of MC68HC16Z1CPV16
Core Processor
CPU16
Core Size
16-Bit
Speed
16MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC16Z1CPV16
Manufacturer:
MOT
Quantity:
5 510
Company:
Part Number:
MC68HC16Z1CPV16
Manufacturer:
FREESCAL
Quantity:
717
Company:
Part Number:
MC68HC16Z1CPV16
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 310 of 500
- Download datasheet (6Mb)
A-26
NOTES:
Num
30A
39A
46A
47A
47B
100
101
102
103
104
105
30
31
33
35
37
39
46
48
53
54
55
70
71
72
73
74
75
76
77
78
1. All AC timing is shown with respect to V
2. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum
allowable t
external clock input duty cycle and minimum t
CLKOUT Low to Data In Invalid (Fast Cycle Hold)
CLKOUT Low to Data In High Impedance
DSACK[1:0] Asserted to Data In Valid
Clock Low to BG Asserted/Negated
BR Asserted to BG Asserted
BGACK Asserted to BG Negated
BG Width Negated
BG Width Asserted
R/W Width Asserted (Write or Read)
R/W Width Asserted (Fast Write or Read Cycle)
Asynchronous Input Setup Time
Asynchronous Input Hold Time
DSACK[1:0] Asserted to BERR, HALT Asserted
Data Out Hold from Clock High
Clock High to Data Out High Impedance
R/W Asserted to Data Bus Impedance Change
Clock Low to Data Bus Driven (Show Cycle)
Data Setup Time to Clock Low (Show Cycle)
Data Hold from Clock Low (Show Cycle)
BKPT Input Setup Time
BKPT Input Hold Time
Mode Select Setup Time (DATA[15:0], MODCLK, BKPT)
Mode Select Hold Time (DATA[15:0], MODCLK, BKPT)
RESET Assertion Time
RESET Rise Time
CLKOUT High to Phase 1 Asserted
CLKOUT High to Phase 2 Asserted
Phase 1 Valid to AS or DS Asserted
Phase 2 Valid to AS or DS Asserted
AS or DS Valid to Phase 1 Negated
AS or DS Negated to Phase 2 Negated
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
Minimum t
Xcyc
period is reduced when the duty cycle of the external clock varies. The relationship between
(V
Table A-18 25.17-MHz AC Timing (Continued)
DD
Xcyc
13
and V
Freescale Semiconductor, Inc.
period = minimum t
For More Information On This Product,
12
Characteristic
DDSYN
ELECTRICAL CHARACTERISTICS
10
= 5.0 Vdc
Go to: www.freescale.com
14
14
14
14
14
IH
9
/V
14
XCHL
IL
7
Xcyc
levels unless otherwise noted.
/ (50% – external clock input duty cycle tolerance).
5%, V
is expressed:
11
7
SS
= 0 Vdc, T
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
BRAGA
t
t
SCLDD
SCLDH
t
CLBAN
SCLDS
t
t
t
CHP1A
CHP2A
P1VSA
P2VSN
SAP1N
SNP2N
t
t
GAGN
t
RWAS
t
t
DOCH
CHDH
t
t
A
CLDH
DABA
RADC
RSTR
BKST
BKHT
RSTA
DADI
CLDI
t
RWA
AIST
AIHT
MSH
t
MSS
GH
GA
= T
L
to T
H
Min
90
55
10
25
10
10
20
—
—
—
—
—
—
8
1
1
2
1
5
0
0
8
8
0
4
3
3
9
9
9
9
)
1
M68HC16 Z SERIES
USER’S MANUAL
Max
—
60
35
19
—
—
—
—
—
—
—
27
—
23
—
19
—
—
—
—
—
—
—
10
34
34
—
—
—
—
2
Unit
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
cyc
cyc
cyc
cyc
cyc
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