MC68HC11E1CFN3 Freescale Semiconductor, MC68HC11E1CFN3 Datasheet - Page 125

• Manufacturer Part Number: MC68HC11E1CFN3
• Description: IC MCU 3MHZ 512 EEPROM 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFN3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 16 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

7.7.4 Serial Communication Status Register
M68HC11E Family — Rev. 5
MOTOROLA
The SCSR provides inputs to the interrupt logic circuits for generation of the SCI
system interrupt.
TDRE — Transmit Data Register Empty Flag
TC — Transmit Complete Flag
RDRF — Receive Data Register Full Flag
IDLE — Idle Line Detected Flag
OR — Overrun Error Flag
This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR with
TDRE set and then writing to SCDR.
This flag is set when the transmitter is idle (no data, preamble, or break
transmission in progress). Clear the TC flag by reading SCSR with TC set and
then writing to SCDR.
This flag is set if a received character is ready to be read from SCDR. Clear the
RDRF flag by reading SCSR with RDRF set and then reading SCDR.
This flag is set if the RxD line is idle. Once cleared, IDLE is not set again until
the RxD line has been active and becomes idle again. The IDLE flag is inhibited
when RWU = 1. Clear IDLE by reading SCSR with IDLE set and then reading
SCDR.
OR is set if a new character is received before a previously received character
is read from SCDR. Clear the OR flag by reading SCSR with OR set and then
reading SCDR.
Address:
Reset:
Read:
Write:
0 = SCDR busy
0 = SCDR empty
0 = Transmitter busy
1 = Transmitter idle
0 = SCDR empty
1 = SCDR full
0 = RxD line active
1 = RxD line idle
0 = No overrun
1 = Overrun detected
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 7-6. Serial Communications Status Register (SCSR)
$102E
TDRE
Bit 7
1
Serial Communications Interface (SCI)
Go to: www.freescale.com
= Unimplemented
TC
6
1
RDRF
5
0
IDLE
4
0
Serial Communications Interface (SCI)
OR
3
0
NF
2
0
FE
1
0
SCI Registers
Data Sheet
Bit 0
0
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