MC68HC908GP32CFB Freescale Semiconductor, MC68HC908GP32CFB Datasheet - Page 200

• Manufacturer Part Number: MC68HC908GP32CFB
• Description: IC MCU 8MHZ 32K FLASH 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP32CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• For Use With: M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Monitor ROM (MON)
15.4.1 Entering Monitor Mode
Technical Data
198
between PTA0 and the host computer. PTA0 is used in a wired-OR
configuration and requires a pullup resistor.
The monitor code has been updated from previous versions of the
monitor code to allow enabling the PLL to generate the internal clock,
provided the reset vector is blank, when the device is being clocked by
a low-frequency crystal. This addition, which is enabled when IRQ is
held low out of reset, is intended to support serial communication/
programming at 9600 baud in monitor mode by stepping up the external
frequency (assumed to be 32.768 kHz) by a fixed amount to generate
the desired internal frequency (2.4576 MHz). Since this feature is
enabled only when IRQ is held low out of reset, it cannot be used when
the reset vector is not blank because entry into monitor mode in this case
requires V
Table 15-1
specified in the table, monitor mode may be entered after a POR and will
allow communication at 9600 baud provided one of the following sets of
conditions is met:
If V
(above condition set 1), the bus frequency is a divide-by-two of the input
clock. If PTC3 is high with V
the bus frequency will be a divide-by-four of the input clock. Holding the
1. If $FFFE and $FFFF does not contain $FF (programmed state):
2. If $FFFE and $FFFF contain $FF (erased state):
3. If $FFFE and $FFFF contain $FF (erased state):
TST
– The external clock is 4.9152 MHz with PTC3 low or
– IRQ = V
– The external clock is 9.8304 MHz
– IRQ = V
– The external clock is 32.768 kHz (crystal)
– IRQ = V
is applied to IRQ and PTC3 is low upon monitor mode entry
9.8304 MHz with PTC3 high
pullup; PLL off)
32.768 kHz to an internal bus frequency of 2.4576 MHz)
TST
shows the pin conditions for entering monitor mode. As
on IRQ.
Monitor ROM (MON)
TST
DD
SS
(this setting initiates the PLL to boost the external
(this can be implemented through the internal IRQ
(PLL off)
TST
applied to IRQ upon monitor mode entry,
MC68HC908GP32
•
MC68HC08GP32
MOTOROLA
—
Rev. 6