MC68HC908JL3CDW Freescale Semiconductor, MC68HC908JL3CDW Datasheet - Page 57

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MC68HC908JL3CDW

Manufacturer Part Number
MC68HC908JL3CDW
Description
IC MCU 8MHZ 4K FLASH 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908JL3CDW

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LED, LVD, POR, PWM
Number Of I /o
23
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 12x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Connectivity
-

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Manufacturer
Quantity
Price
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WSI
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8
Part Number:
MC68HC908JL3CDW
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
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6.4.4 Program Counter
6.4.5 Condition Code Register
MC68H(R)C908JL3
Freescale Semiconductor
NOTE:
Rev. 1.1
The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct
address (page 0) space. For correct operation, the stack pointer must
point only to RAM locations.
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
Reset:
Reset:
Read:
Read:
Write:
Write:
Bit
Bit
15
15
0
14
14
Central Processor Unit (CPU)
0
13
13
0
Figure 6-5. Program Counter (PC)
Figure 6-4. Stack Pointer (SP)
12
12
0
11
11
0
Loaded with Vector from $FFFE and $FFFF
10
10
0
9
9
0
8
8
0
7
1
7
6
6
1
Central Processor Unit (CPU)
5
5
1
4
4
1
3
1
3
Technical Data
2
2
1
1
1
1
Bit
Bit
0
0
55
1

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