MC68HC908JL3CDW Freescale Semiconductor, MC68HC908JL3CDW Datasheet - Page 107
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MC68HC908JL3CDW
Manufacturer Part Number
MC68HC908JL3CDW
Description
IC MCU 8MHZ 4K FLASH 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68HC908JK1CDW.pdf
(212 pages)
Specifications of MC68HC908JL3CDW
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LED, LVD, POR, PWM
Number Of I /o
23
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 12x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC908JL3CDW
Manufacturer:
WSI
Quantity:
8
Part Number:
MC68HC908JL3CDW
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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MC68H(R)C908JL3
Freescale Semiconductor
—
Rev. 1.1
If V
(Table 9-1
external clock input to OSC1. If PTB3 is high with V
IRQ1 upon monitor mode entry
frequency is a divide-by-four of the external clock input to OSC1. Holding
the PTB3 pin low when entering monitor mode causes a bypass of a
divide-by-two stage at the oscillator only if V
In this event, the OSCOUT frequency is equal to the 2OSCOUT
frequency, and OSC1 input directly generates internal bus clocks. In this
case, the OSC1 signal must have a 50% duty cycle at maximum bus
frequency.
Entering monitor mode with V
long as V
7. System Integration Module (SIM)
operation.)
If entering monitor mode without high voltage on IRQ1 and reset vector
being blank ($FFFE and $FFFF)
applied voltage is V
including the PTB3 frequency divisor selection, are not in effect. This is
to reduce circuit requirements when performing in-circuit programming.
Entering monitor mode with the reset vector being blank, the COP is
always disabled regardless of the state of IRQ1 or the RST.
Figure
the reset vector is blank and IRQ1 = V
(XTALCLK or RCCCLK) of 9.8304MHz is required for a baud rate of
9600.
DD
+V
9-2. shows a simplified diagram of the monitor mode entry when
DD
HI
condition set 1), the bus frequency is a divide-by-two of the
is applied to IRQ1 and PTB3 is low upon monitor mode entry
+ V
Monitor ROM (MON)
HI
is applied to either the IRQ1 or the RST. (See
DD
), then all port B pin requirements and conditions,
DD
(Table 9-1
+ V
(Table 9-1
HI
for more information on modes of
DD
on IRQ1, the COP is disabled as
. An oscillator frequency
condition set 2), the bus
DD
condition set 3, where
+V
HI
DD
is applied to IRQ1.
Monitor ROM (MON)
+V
HI
Technical Data
applied to
Section
105
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