UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 94
UPSD3234A-40U6T
Manufacturer Part Number
UPSD3234A-40U6T
Description
IC MCU 8032 64KB FLASH 80TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet
1.UPSD3234A-40U6T.pdf
(189 pages)
Specifications of UPSD3234A-40U6T
Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, UART/USART, USB
Peripherals
LVR, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
288KB (288K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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DDC interface
16.4
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DDC2B protocol
DDC2B is constructed based on the Philips I
PC host is fixed as the master and the monitor is always regarded as the slave. Both master
and slave can be operated as a transmitter or receiver, but the master device determines
which mode is activated. In this protocol, address pointer is also used.
According to DDC2B specification, A0 (for WRITE mode) and A1 (for READ mode) are
assigned as the default address of monitors.
The reception of the incoming data in WRITE mode or the updating of the outgoing data in
READ mode should be finished within the specified time limit. If software in the slave’s side
cannot react to the master in time, based on I
inhibit the further action from the master. The transaction can be proceeded in either byte or
burst format.
Figure 42. Conceptual structure of the DDC interface
DDC2B/DDC2AB
command received
DDC2B/DDC2AB
Utilities
SWENB = 1
Service Routines
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
I2C interface
(H/W)
I2C
Check Mode flag in DDCCON
Mode = 1 Mode = 1 Mode = 0
DDC Interrupt
vector address
(
0023H
2
DDC2B
Utilities
2
C interface. However, in the level of DDC2B,
C protocol, SCL pin can be stretched low to
DDC2B
SWENB =1
)
DDC Transmitter
DDC1.
Utilities
(H/W)
D DC2B
SWENB =0
AI06645
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