UPSD3454E-40T6 STMicroelectronics, UPSD3454E-40T6 Datasheet - Page 242
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UPSD3454E-40T6
Manufacturer Part Number
UPSD3454E-40T6
Description
MCU 8BIT 8032 256K FLASH 52-TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet
1.UPSD3422EV-40U6.pdf
(300 pages)
Specifications of UPSD3454E-40T6
Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
288KB (288K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-TQFP, 52-VQFP
For Use With
497-5518 - EVAL BOARD RFID READER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
UPSD3454E-40T6
Manufacturer:
STMicroelectronics
Quantity:
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Table 193. Port B pin drive select register (address = csiop + offset 09h)
1. For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS push/pull.
2. Default state for register is 00h after reset or power-up.
Table 194. Port C pin drive select register (address = csiop + offset 16h)
1. For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS push/pull
2. Default state for register is 00h after reset or power-up
Table 195. Port D pin drive select register (address = csiop + offset 17h)
1. For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS push/pull
2. Default state for register is 00h after reset or power-up
3. Pin is not available on 52-pin UPSD34xx devices
Table 196. Port A enable out register
1. Port A not available on 52-pin UPSD34xx devices
2. For each bit, 1 = pin drive is enabled as an output, 0 = pin drive is off (high-impedance, pin used as input)
Table 197. Port B enable out register (address = csiop + offset 0Dh)
1. For each bit, 1 = pin drive is enabled as an output, 0 = pin drive is off (high-impedance, pin used as input)
Table 198. Port C enable out register (address = csiop + offset 1Ah)
1. For each bit, 1 = pin drive is enabled as an output, 0 = pin drive is off (high-impedance, pin used as input)
Table 199. Port D enable out register (address = csiop + offset 1Bh)
1. For each bit, 1 = pin drive is enabled as an output, 0 = pin drive is off (high-impedance, pin used as input)
2. Pin is not available on 52-pin UPSD34xx devices
open drain
open drain
PC7 OE
PB7 OE
PA7 OE
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
PB7
PC7
N/A
N/A
open drain
PB6 OE
PA6 OE
(JTAG)
(JTAG)
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
PB6
N/A
N/A
N/A
N/A
open drain
PB5 OE
PA5 OE
(JTAG)
(JTAG)
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
PB5
N/A
N/A
N/A
N/A
open drain
open drain
PB4 OE
PC4 OE
PA4 OE
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
PC4
PB4
N/A
N/A
(1) (2)
UPSD3422, UPSD3433, UPSD3434, UPSD3454
(address = csiop + offset 0Ch)
open drain
slew rate
PC3 OE
PB3 OE
PA3 OE
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
PB3
PC3
N/A
N/A
open drain
PD2 OE
slew rate
slew rate
PC2 OE
PB2 OE
PA2 OE
PD2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
PB2
PC2
(3)
(2)
slew rate
slew rate
PB1 OE
PD1 OE
PA1 OE
(JTAG)
(JTAG)
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
PB1
PD1
N/A
N/A
(1)
(1)
(1)
(1) (2)
(1) (2)
(1) (2)
slew rate
PB0 OE
PA0 OE
(JTAG)
(JTAG)
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
PB0
N/A
N/A
N/A
N/A
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