STR910FW32X6 STMicroelectronics, STR910FW32X6 Datasheet - Page 22

• Manufacturer Part Number: STR910FW32X6
• Description: MCU 256K FLASH 64K SRAM CAN
• Manufacturer: STMicroelectronics
• Series: STR9r

Specifications of STR910FW32X6

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• For Use With: 497-8268 - BOARD EVAL FOR EVAL-STR910MCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2MCBSTR9 - BOARD EVAL STM STR9 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5059; 497-5059-2; 497-5059-2; STR910FW32X6T

Functional overview
2.15.1 In-system-programming
2.15.2 Boundary scan
2.15.3 CPU debug
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Figure 3.
The JTAG interface is used to program or erase all memory areas of the STR91xF device. The
pin RESET_INn must be asserted during ISP to prevent the CPU from fetching invalid
instructions while the Flash memories are being programmed.
Note that the 32 bytes of OTP memory locations cannot be erased by any means once
programmed by JTAG ISP or the CPU.
Standard JTAG boundary scan testing compliant with IEEE-1149.1 is available on the majority
of pins of the STR91xF for circuit board test during manufacture of the end product. STR91xF
pins that are not serviced by boundary scan are the following:
●
●
●
The ARM966E-S CPU core has standard ARM EmbeddedICE-RT logic, allowing the STR91xF
to be debugged through the JTAG interface. This provides advanced debugging features
making it easier to develop application firmware, operating systems, and the hardware itself.
JTRSTn
JRTCK
JTDO
JTMS
JTCK
JTDI
JTAG pins JTCK, JTMS, JTDI, JTDO, JTRSTn, JRTCK
Oscillator input pins X1_CPU, X2_CPU, X1_RTC, X2_RTC
Tamper detect input pin TAMPER_IN (128-pin packages only)
JTAG chaining inside the STR91xF
TDO
MAIN FLASH
TDI
JTAG TAP CONTROLLER #1
JTAG TAP CONTROLLER #3
TMS
TMS
BOUNDARY SCAN
TCK
TCK
SECONDARY FLASH
TRST
TRST
TDO
TDI
register length
Instruction
BURST FLASH
MEMORY DIE
is 8 bits
TDI
JTAG
JTAG TAP CONTROLLER #2
TRST
CPU DEBUG
TCK
TMS
TDO
ARM966ES DIE
5 bits for TAP #1
4 bits for TAP #2
register length:
Instruction
JTAG
STR91xF
STR91xx