UPSD3433E-40T6 STMicroelectronics, UPSD3433E-40T6 Datasheet - Page 123
UPSD3433E-40T6
Manufacturer Part Number
UPSD3433E-40T6
Description
MCU 8BIT 8032 128KB FLASH 52TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet
1.UPSD3422EV-40U6.pdf
(300 pages)
Specifications of UPSD3433E-40T6
Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-TQFP, 52-VQFP
For Use With
497-5518 - EVAL BOARD RFID READER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-4906
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPSD3433E-40T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
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UPSD3422, UPSD3433, UPSD3434, UPSD3454
23
23.1
I
UPSD34xx devices support one serial I
channel, having a bidirectional data signal (SDA, pin P3.6) and a clock signal (SCL, pin
P3.7) based on open-drain line drivers, requiring external pull-up resistors, R
typical value of 4.7kΩ (see
I
Byte-wide data is transferred, MSB first, between a Master device and a Slave device on two
wires. More than one bus Master is allowed, but only one Master may control the bus at any
given time. Data is not lost when another Master requests the use of a busy bus because
I
and generates the clock that permits the transfer. Once a transfer is initiated by the Master,
any device addressed is considered a Slave. Automatic clock synchronization allows I
devices with different bit rates to communicate on the same physical bus. A single device
can play the role of Master or Slave, or a single device can be a Slave only. Each Slave
device on the bus has a unique address, and a general broadcast address is also available.
A Master or Slave device has the ability to suspend data transfers if the device needs more
time to transmit or receive data.
This I
●
●
●
●
●
Figure 40. Typical I
1. For 3.3 V system, connect R
2
2
2
C supports collision detection and arbitration. The bus Master initiates all data movement
C interface main features
I 2 C bus
C interface
Serial I/O Engine (SIOE): serial/parallel conversion; bus arbitration; clock generation
and synchronization; and handshaking are all performed in hardware
Interrupt or Polled operation
Multi-master capability
7-bit Addressing
Supports standard speed I
and high-speed mode I
2
C interface has the following features:
SDA
SCL
SDA/P3.6 SCL/P3.7
uPSD34XX(V)
V CC or V DD (1)
2
C bus configuration
P
Figure
to 3.3 V V
2
C (401KHz to 833kHz)
R P
2
C (SCL up to 100kHz), fast mode I
40).
CC
. For 5.0 V system, connect R
R P
2
C interface. This is a two-wire communication
Device with I 2 C
interface
Device with I 2 C
Interface
P
to 5.0 V V
2
C (101KHz to 400kHz),
DD
Device with I 2 C
.
interface
P
, each with a
I
2
C interface
AI09623c
123/300
2
C
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