UPSD3433E-40U6 STMicroelectronics, UPSD3433E-40U6 Datasheet - Page 175
UPSD3433E-40U6
Manufacturer Part Number
UPSD3433E-40U6
Description
MCU 8BIT 8032 128KB FLASH 80TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet
1.UPSD3422EV-40U6.pdf
(300 pages)
Specifications of UPSD3433E-40U6
Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
For Use With
497-5518 - EVAL BOARD RFID READER497-5218 - KIT DEVELOPMENT FOR UPSD3400497-2381 - CABLE PROGRAMMER FLASH LINK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-4907
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPSD3433E-40U6
Manufacturer:
DENSO
Quantity:
83
Company:
Part Number:
UPSD3433E-40U6
Manufacturer:
STMicroelectronics
Quantity:
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- Current page: 175 of 300
- Download datasheet (3Mb)
UPSD3422, UPSD3433, UPSD3434, UPSD3454
●
Table 130. USB FIFO base address high register (UBASEH 0F3h, reset value 00h)
Table 131. UBASEH register bit definition
Table 132. USB FIFO base address low register (UBASEL 0F4h, reset value 00h)
Table 133. UBASEL register bit definition
Bit 7
7:6
5:0
Bit
BASEADDR[7:6]
Bit 7
7:0
USB FIFO base address high and low registers (UBASEH and UBASEL)
All 10 Endpoint FIFOs share the same 64-byte address range. The 16-bit base
address for the FIFOs is specified using the USB base address registers (see
Table 130
page
addressing the 64-bytes of XDATA space starting with the base address specified in the
base address registers. The base address is a 64-byte segment where the lower 6 bits
of the base register are hardwired to '0.'
Important note: The USB FIFO base address must be set to an open 64-byte segment
in the XDATA space. Care should be taken to ensure that there is no overlap of
addresses between the USB FIFOs and the flash memory, SRAM, csiop registers, and
anything else accessed in the XDATA space. While the logic in the PSD module
handles overlap of flash memory, SRAM, and the csiop registers with a fixed priority
(see
case with the USB FIFOs. Unpredictable results as well as potential damage to the
device may occur if there is an overlap of addresses.
Bit
Section 28.1: PSD module functional description on page
172) selects the direction and the Endpoint for the FIFO that is accessed when
BASEADDR
BASEADDR
Symbol
BASEADDR
[7:6]
[5:0]
Bit 6
Symbol
and
[15:8]
Bit 6
Table
R/W
R/W
132). The USB endpoint select register (see
Bit 5
R
0
Bit 5
R/W
R/W
Bits 7 and 6 of the 16-bit base address for the USB FIFOs to
be mapped in XDATA space
Hardwired '0'
BASEADDR[15:8]
Bit 4
The upper 8 bits of the 16-bit base address for USB FIFOs
to be mapped in XDATA space
0
Bit 4
Bit 3
0
Bit 3
Definition
Definition
Bit 2
Bit 2
0
192), this is not the
Table 124 on
Bit 1
Bit 1
0
USB interface
Bit 0
Bit 0
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0
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